Dissertation/ Thesis
Behavior characterization of the shared last-level cache in a chip multiprocessor
| Τίτλος: | Behavior characterization of the shared last-level cache in a chip multiprocessor |
|---|---|
| Συγγραφείς: | Benedicte Illescas, Pedro |
| Συνεισφορές: | Llaberia Griñó, José M., Monreal Arnal, Teresa |
| Στοιχεία εκδότη: | Universitat Politècnica de Catalunya |
| Έτος έκδοσης: | 2014 |
| Συλλογή: | Universitat Politècnica de Catalunya, BarcelonaTech: UPCommons - Global access to UPC knowledge |
| Θεματικοί όροι: | Àrees temàtiques de la UPC::Informàtica, Multiprocessors, multiprocessador, cache, reemplaçament, multiprocessor, replacement, Multiprocessadors |
| Περιγραφή: | [CATALÀ] Aquest projecte consisteix a analitzar diferents aspectes de la jerarquia de memòria i entendre la seva influència al rendiment del sistema. Els aspectes que s'analitzaran són els algorismes de reemplaçament, els esquemes de mapeig de memòria i les polítiques de pàgina de memòria. ; [ANGLÈS] This project consists in analyzing different aspects of the memory hierarchy and understanding its influence in the overall system performance. The aspects that will be analyzed are cache replacement algorithms, memory mapping schemes and memory page policies. |
| Τύπος εγγράφου: | master thesis |
| Περιγραφή αρχείου: | application/pdf |
| Γλώσσα: | English |
| Relation: | https://hdl.handle.net/2099.1/23771; 101369 |
| Διαθεσιμότητα: | https://hdl.handle.net/2099.1/23771 |
| Rights: | Open Access |
| Αριθμός Καταχώρησης: | edsbas.8339CC42 |
| Βάση Δεδομένων: | BASE |
| FullText | Text: Availability: 0 CustomLinks: – Url: https://hdl.handle.net/2099.1/23771# Name: EDS - BASE (ns324271) Category: fullText Text: View record from BASE |
|---|---|
| Header | DbId: edsbas DbLabel: BASE An: edsbas.8339CC42 RelevancyScore: 769 AccessLevel: 3 PubType: Dissertation/ Thesis PubTypeId: dissertation PreciseRelevancyScore: 768.644287109375 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Behavior characterization of the shared last-level cache in a chip multiprocessor – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Benedicte+Illescas%2C+Pedro%22">Benedicte Illescas, Pedro</searchLink> – Name: Author Label: Contributors Group: Au Data: Llaberia Griñó, José M.<br />Monreal Arnal, Teresa – Name: Publisher Label: Publisher Information Group: PubInfo Data: Universitat Politècnica de Catalunya – Name: DatePubCY Label: Publication Year Group: Date Data: 2014 – Name: Subset Label: Collection Group: HoldingsInfo Data: Universitat Politècnica de Catalunya, BarcelonaTech: UPCommons - Global access to UPC knowledge – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Àrees+temàtiques+de+la+UPC%3A%3AInformàtica%22">Àrees temàtiques de la UPC::Informàtica</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprocessors%22">Multiprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22multiprocessador%22">multiprocessador</searchLink><br /><searchLink fieldCode="DE" term="%22cache%22">cache</searchLink><br /><searchLink fieldCode="DE" term="%22reemplaçament%22">reemplaçament</searchLink><br /><searchLink fieldCode="DE" term="%22multiprocessor%22">multiprocessor</searchLink><br /><searchLink fieldCode="DE" term="%22replacement%22">replacement</searchLink><br /><searchLink fieldCode="DE" term="%22Multiprocessadors%22">Multiprocessadors</searchLink> – Name: Abstract Label: Description Group: Ab Data: [CATALÀ] Aquest projecte consisteix a analitzar diferents aspectes de la jerarquia de memòria i entendre la seva influència al rendiment del sistema. Els aspectes que s'analitzaran són els algorismes de reemplaçament, els esquemes de mapeig de memòria i les polítiques de pàgina de memòria. ; [ANGLÈS] This project consists in analyzing different aspects of the memory hierarchy and understanding its influence in the overall system performance. The aspects that will be analyzed are cache replacement algorithms, memory mapping schemes and memory page policies. – Name: TypeDocument Label: Document Type Group: TypDoc Data: master thesis – Name: Format Label: File Description Group: SrcInfo Data: application/pdf – Name: Language Label: Language Group: Lang Data: English – Name: NoteTitleSource Label: Relation Group: SrcInfo Data: https://hdl.handle.net/2099.1/23771; 101369 – Name: URL Label: Availability Group: URL Data: https://hdl.handle.net/2099.1/23771 – Name: Copyright Label: Rights Group: Cpyrght Data: Open Access – Name: AN Label: Accession Number Group: ID Data: edsbas.8339CC42 |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edsbas&AN=edsbas.8339CC42 |
| RecordInfo | BibRecord: BibEntity: Languages: – Text: English Subjects: – SubjectFull: Àrees temàtiques de la UPC::Informàtica Type: general – SubjectFull: Multiprocessors Type: general – SubjectFull: multiprocessador Type: general – SubjectFull: cache Type: general – SubjectFull: reemplaçament Type: general – SubjectFull: multiprocessor Type: general – SubjectFull: replacement Type: general – SubjectFull: Multiprocessadors Type: general Titles: – TitleFull: Behavior characterization of the shared last-level cache in a chip multiprocessor Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Benedicte Illescas, Pedro – PersonEntity: Name: NameFull: Llaberia Griñó, José M. – PersonEntity: Name: NameFull: Monreal Arnal, Teresa IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 01 Type: published Y: 2014 Identifiers: – Type: issn-locals Value: edsbas – Type: issn-locals Value: edsbas.oa |
| ResultId | 1 |