Bibliographic Details
| Title: |
Applying formal verification techniques to verify a Fetch Unit |
| Authors: |
Jiménez González, Adrián |
| Contributors: |
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Moreno Vega, Alberto, Espasa Sans, Roger |
| Publisher Information: |
Universitat Politècnica de Catalunya |
| Publication Year: |
2024 |
| Collection: |
Universitat Politècnica de Catalunya, BarcelonaTech: UPCommons - Global access to UPC knowledge |
| Subject Terms: |
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Computer programs--Testing, Verificació Formal, Assercions, Proves, Complexitat, Tècniques de reducció, Formal Verification, Assertions, Proofs, Complexity, Reduction Techniques, Programes d'ordinador--Verificació |
| Description: |
The fetch unit of a GPP is a difficult block to verify. The complexity of the problem stems from the size of the state (cache, pipeline, etc.). Formal verification techniques, traditionally, have difficulty handling problems with large amounts of memory. We will explore different approaches to deal with these limitations such that we are able to reduce the wall time needed by the Formal Verification tools. This project covers the design and implementation of a Testbench for Formal Verification. In addition, it introduces different techniques and configurations to reduce the complexity of the Design Under Test and how they are applied into our Formal Verification Testbench. Finally, the performance impact of each technique is analyzed at the end of the document. |
| Document Type: |
master thesis |
| File Description: |
application/pdf |
| Language: |
English |
| Relation: |
https://hdl.handle.net/2117/418186; 188837 |
| Availability: |
https://hdl.handle.net/2117/418186 |
| Rights: |
Open Access |
| Accession Number: |
edsbas.117F85A3 |
| Database: |
BASE |