Academic Journal
View in EDS

A Model Checking-Based Method of Functional Test Generation for HDL Descriptions

Bibliographic Details
Title: A Model Checking-Based Method of Functional Test Generation for HDL Descriptions
Authors: LEBEDEV M.S., SMOLOV S.A.
Source: Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
Publisher Information: Institute for System Programming of the Russian Academy of Sciences, 2016.
Publication Year: 2016
Subject Terms: охраняемое действие, расширенный конечный автомат, статический анализ, функциональная верификация, Electronic computers. Computer science, генерация тестов, цифровая аппаратура, QA75.5-76.95, HARDWARE DESIGN,FUNCTIONAL VERIFICATION,STATIC ANALYSIS,TEST GENERATION,GUARDED ACTION,HIGH-LEVEL DECISION DIAGRAM,EXTENDED FINITE STATE MACHINE,MODEL CHECKING,ЦИФРОВАЯ АППАРАТУРА,ФУНКЦИОНАЛЬНАЯ ВЕРИФИКАЦИЯ,СТАТИЧЕСКИЙ АНАЛИЗ,ГЕНЕРАЦИЯ ТЕСТОВ,ОХРАНЯЕМОЕ ДЕЙСТВИЕ,ВЫСОКОУРОВНЕВАЯ РЕШАЮЩАЯ ДИАГРАММА,РАСШИРЕННЫЙ КОНЕЧНЫЙ АВТОМАТ,ПРОВЕРКА МОДЕЛИ, высокоуровневая решающая диаграмма, проверка модели
Description: Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is proposed and compared to existing solutions. Automated model extraction from the hardware design’s source code is used. Supported HDLs include VHDL and Verilog. Several kinds of models are used at different steps of the test generation method: guarded action decision diagram (GADD), high-level decision diagram (HLDD) and extended finite-state machine (EFSM). The high-level decision diagram model (which is extracted from the GADD model) is used as a functional model. The extended finite-state machine model is used as a coverage model. The aim of test generation is to cover all the transitions of the extended finite state machine model. Such criterion leads to the high HDL source code coverage. Specifications based on transition and state constraints of the EFSM are extracted for this purpose. Later, the functional model and the specifications are automatically translated into the input format of the nuXmv model checking tool. nuXmv performs model checking and generates counterexamples. These counterexamples are translated to functional tests that can be simulated by the HDL simulator. The proposed method has been implemented as a part of the HDL Retrascope framework. Experiments show that the method can generate shorter tests than the FATE and RETGA methods providing the same or better source code coverage.
Document Type: Article
Other literature type
File Description: text/html
ISSN: 2220-6426
2079-8156
DOI: 10.15514/ispras-2016-28(4)-3
Access URL: http://ispras.ru/proceedings/docs/2016/28/4/isp_28_2016_4_41.pdf
https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae
https://ispranproceedings.elpub.ru/jour/article/download/138/75
https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae
https://ispranproceedings.elpub.ru/jour/article/view/138
https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions
https://www.ispras.ru/en/proceedings/isp_28_2016_4/isp_28_2016_4_41/
https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions/pdf
http://cyberleninka.ru/article_covers/16937636.png
http://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions
Rights: CC BY
Accession Number: edsair.doi.dedup.....a6c66847f2c2bc2ec8bafce6c6f094ef
Database: OpenAIRE
FullText Text:
  Availability: 0
CustomLinks:
  – Url: https://explore.openaire.eu/search/publication?articleId=doi_dedup___%3A%3Aa6c66847f2c2bc2ec8bafce6c6f094ef
    Name: EDS - OpenAIRE (ns324271)
    Category: fullText
    Text: View record at OpenAIRE
  – Url: https://resolver.ebsco.com/c/fiv2js/result?sid=EBSCO:edsair&genre=article&issn=22206426&ISBN=&volume=28&issue=&date=20160101&spage=41&pages=41-56&title=Proceedings of the Institute for System Programming of the RAS&atitle=A%20Model%20Checking-Based%20Method%20of%20Functional%20Test%20Generation%20for%20HDL%20Descriptions&aulast=LEBEDEV%20M.S.&id=DOI:10.15514/ispras-2016-28(4)-3
    Name: Full Text Finder (for New FTF UI) (ns324271)
    Category: fullText
    Text: Full Text Finder
    MouseOverText: Full Text Finder
Header DbId: edsair
DbLabel: OpenAIRE
An: edsair.doi.dedup.....a6c66847f2c2bc2ec8bafce6c6f094ef
RelevancyScore: 837
AccessLevel: 3
PubType: Academic Journal
PubTypeId: academicJournal
PreciseRelevancyScore: 837.438598632813
IllustrationInfo
Items – Name: Title
  Label: Title
  Group: Ti
  Data: A Model Checking-Based Method of Functional Test Generation for HDL Descriptions
– Name: Author
  Label: Authors
  Group: Au
  Data: <searchLink fieldCode="AR" term="%22LEBEDEV+M%2ES%2E%22">LEBEDEV M.S.</searchLink><br /><searchLink fieldCode="AR" term="%22SMOLOV+S%2EA%2E%22">SMOLOV S.A.</searchLink>
– Name: TitleSource
  Label: Source
  Group: Src
  Data: Труды Института системного программирования РАН, Vol 28, Iss 4, Pp 41-56 (2018)
– Name: Publisher
  Label: Publisher Information
  Group: PubInfo
  Data: Institute for System Programming of the Russian Academy of Sciences, 2016.
– Name: DatePubCY
  Label: Publication Year
  Group: Date
  Data: 2016
– Name: Subject
  Label: Subject Terms
  Group: Su
  Data: <searchLink fieldCode="DE" term="%22охраняемое+действие%22">охраняемое действие</searchLink><br /><searchLink fieldCode="DE" term="%22расширенный+конечный+автомат%22">расширенный конечный автомат</searchLink><br /><searchLink fieldCode="DE" term="%22статический+анализ%22">статический анализ</searchLink><br /><searchLink fieldCode="DE" term="%22функциональная+верификация%22">функциональная верификация</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+computers%2E+Computer+science%22">Electronic computers. Computer science</searchLink><br /><searchLink fieldCode="DE" term="%22генерация+тестов%22">генерация тестов</searchLink><br /><searchLink fieldCode="DE" term="%22цифровая+аппаратура%22">цифровая аппаратура</searchLink><br /><searchLink fieldCode="DE" term="%22QA75%2E5-76%2E95%22">QA75.5-76.95</searchLink><br /><searchLink fieldCode="DE" term="%22HARDWARE+DESIGN%2CFUNCTIONAL+VERIFICATION%2CSTATIC+ANALYSIS%2CTEST+GENERATION%2CGUARDED+ACTION%2CHIGH-LEVEL+DECISION+DIAGRAM%2CEXTENDED+FINITE+STATE+MACHINE%2CMODEL+CHECKING%2CЦИФРОВАЯ+АППАРАТУРА%2CФУНКЦИОНАЛЬНАЯ+ВЕРИФИКАЦИЯ%2CСТАТИЧЕСКИЙ+АНАЛИЗ%2CГЕНЕРАЦИЯ+ТЕСТОВ%2CОХРАНЯЕМОЕ+ДЕЙСТВИЕ%2CВЫСОКОУРОВНЕВАЯ+РЕШАЮЩАЯ+ДИАГРАММА%2CРАСШИРЕННЫЙ+КОНЕЧНЫЙ+АВТОМАТ%2CПРОВЕРКА+МОДЕЛИ%22">HARDWARE DESIGN,FUNCTIONAL VERIFICATION,STATIC ANALYSIS,TEST GENERATION,GUARDED ACTION,HIGH-LEVEL DECISION DIAGRAM,EXTENDED FINITE STATE MACHINE,MODEL CHECKING,ЦИФРОВАЯ АППАРАТУРА,ФУНКЦИОНАЛЬНАЯ ВЕРИФИКАЦИЯ,СТАТИЧЕСКИЙ АНАЛИЗ,ГЕНЕРАЦИЯ ТЕСТОВ,ОХРАНЯЕМОЕ ДЕЙСТВИЕ,ВЫСОКОУРОВНЕВАЯ РЕШАЮЩАЯ ДИАГРАММА,РАСШИРЕННЫЙ КОНЕЧНЫЙ АВТОМАТ,ПРОВЕРКА МОДЕЛИ</searchLink><br /><searchLink fieldCode="DE" term="%22высокоуровневая+решающая+диаграмма%22">высокоуровневая решающая диаграмма</searchLink><br /><searchLink fieldCode="DE" term="%22проверка+модели%22">проверка модели</searchLink>
– Name: Abstract
  Label: Description
  Group: Ab
  Data: Automated test generation is a promising direction in hardware verification research area. Functional test generation methods based on models are widespread at the moment. In this paper, a functional test generation method based on model checking is proposed and compared to existing solutions. Automated model extraction from the hardware design’s source code is used. Supported HDLs include VHDL and Verilog. Several kinds of models are used at different steps of the test generation method: guarded action decision diagram (GADD), high-level decision diagram (HLDD) and extended finite-state machine (EFSM). The high-level decision diagram model (which is extracted from the GADD model) is used as a functional model. The extended finite-state machine model is used as a coverage model. The aim of test generation is to cover all the transitions of the extended finite state machine model. Such criterion leads to the high HDL source code coverage. Specifications based on transition and state constraints of the EFSM are extracted for this purpose. Later, the functional model and the specifications are automatically translated into the input format of the nuXmv model checking tool. nuXmv performs model checking and generates counterexamples. These counterexamples are translated to functional tests that can be simulated by the HDL simulator. The proposed method has been implemented as a part of the HDL Retrascope framework. Experiments show that the method can generate shorter tests than the FATE and RETGA methods providing the same or better source code coverage.
– Name: TypeDocument
  Label: Document Type
  Group: TypDoc
  Data: Article<br />Other literature type
– Name: Format
  Label: File Description
  Group: SrcInfo
  Data: text/html
– Name: ISSN
  Label: ISSN
  Group: ISSN
  Data: 2220-6426<br />2079-8156
– Name: DOI
  Label: DOI
  Group: ID
  Data: 10.15514/ispras-2016-28(4)-3
– Name: URL
  Label: Access URL
  Group: URL
  Data: <link linkTarget="URL" linkTerm="http://ispras.ru/proceedings/docs/2016/28/4/isp_28_2016_4_41.pdf" linkWindow="_blank">http://ispras.ru/proceedings/docs/2016/28/4/isp_28_2016_4_41.pdf</link><br /><link linkTarget="URL" linkTerm="https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae" linkWindow="_blank">https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae</link><br /><link linkTarget="URL" linkTerm="https://ispranproceedings.elpub.ru/jour/article/download/138/75" linkWindow="_blank">https://ispranproceedings.elpub.ru/jour/article/download/138/75</link><br /><link linkTarget="URL" linkTerm="https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae" linkWindow="_blank">https://doaj.org/article/db5cd6bc2a3c4fd88d1b58c262c5cfae</link><br /><link linkTarget="URL" linkTerm="https://ispranproceedings.elpub.ru/jour/article/view/138" linkWindow="_blank">https://ispranproceedings.elpub.ru/jour/article/view/138</link><br /><link linkTarget="URL" linkTerm="https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions" linkWindow="_blank">https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions</link><br /><link linkTarget="URL" linkTerm="https://www.ispras.ru/en/proceedings/isp_28_2016_4/isp_28_2016_4_41/" linkWindow="_blank">https://www.ispras.ru/en/proceedings/isp_28_2016_4/isp_28_2016_4_41/</link><br /><link linkTarget="URL" linkTerm="https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions/pdf" linkWindow="_blank">https://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions/pdf</link><br /><link linkTarget="URL" linkTerm="http://cyberleninka.ru/article_covers/16937636.png" linkWindow="_blank">http://cyberleninka.ru/article_covers/16937636.png</link><br /><link linkTarget="URL" linkTerm="http://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions" linkWindow="_blank">http://cyberleninka.ru/article/n/a-model-checking-based-method-of-functional-test-generation-for-hdl-descriptions</link>
– Name: Copyright
  Label: Rights
  Group: Cpyrght
  Data: CC BY
– Name: AN
  Label: Accession Number
  Group: ID
  Data: edsair.doi.dedup.....a6c66847f2c2bc2ec8bafce6c6f094ef
PLink https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edsair&AN=edsair.doi.dedup.....a6c66847f2c2bc2ec8bafce6c6f094ef
RecordInfo BibRecord:
  BibEntity:
    Identifiers:
      – Type: doi
        Value: 10.15514/ispras-2016-28(4)-3
    Languages:
      – Text: Undetermined
    PhysicalDescription:
      Pagination:
        PageCount: 16
        StartPage: 41
    Subjects:
      – SubjectFull: охраняемое действие
        Type: general
      – SubjectFull: расширенный конечный автомат
        Type: general
      – SubjectFull: статический анализ
        Type: general
      – SubjectFull: функциональная верификация
        Type: general
      – SubjectFull: Electronic computers. Computer science
        Type: general
      – SubjectFull: генерация тестов
        Type: general
      – SubjectFull: цифровая аппаратура
        Type: general
      – SubjectFull: QA75.5-76.95
        Type: general
      – SubjectFull: HARDWARE DESIGN,FUNCTIONAL VERIFICATION,STATIC ANALYSIS,TEST GENERATION,GUARDED ACTION,HIGH-LEVEL DECISION DIAGRAM,EXTENDED FINITE STATE MACHINE,MODEL CHECKING,ЦИФРОВАЯ АППАРАТУРА,ФУНКЦИОНАЛЬНАЯ ВЕРИФИКАЦИЯ,СТАТИЧЕСКИЙ АНАЛИЗ,ГЕНЕРАЦИЯ ТЕСТОВ,ОХРАНЯЕМОЕ ДЕЙСТВИЕ,ВЫСОКОУРОВНЕВАЯ РЕШАЮЩАЯ ДИАГРАММА,РАСШИРЕННЫЙ КОНЕЧНЫЙ АВТОМАТ,ПРОВЕРКА МОДЕЛИ
        Type: general
      – SubjectFull: высокоуровневая решающая диаграмма
        Type: general
      – SubjectFull: проверка модели
        Type: general
    Titles:
      – TitleFull: A Model Checking-Based Method of Functional Test Generation for HDL Descriptions
        Type: main
  BibRelationships:
    HasContributorRelationships:
      – PersonEntity:
          Name:
            NameFull: LEBEDEV M.S.
      – PersonEntity:
          Name:
            NameFull: SMOLOV S.A.
    IsPartOfRelationships:
      – BibEntity:
          Dates:
            – D: 01
              M: 01
              Type: published
              Y: 2016
          Identifiers:
            – Type: issn-print
              Value: 22206426
            – Type: issn-print
              Value: 20798156
            – Type: issn-locals
              Value: edsair
            – Type: issn-locals
              Value: edsairFT
          Numbering:
            – Type: volume
              Value: 28
          Titles:
            – TitleFull: Proceedings of the Institute for System Programming of the RAS
              Type: main
ResultId 1