Bibliographic Details
| Title: |
Minimizing Leakage Current & Ground Rail Fluctuations in 1-Bit 8t Full Adder Circuit Using Mtcmos Techniques |
| Authors: |
Yash Pathak, Dharmendra Kumar Jhariya |
| Source: |
2024 First International Conference on Electronics, Communication and Signal Processing (ICECSP). :1-5 |
| Publisher Information: |
IEEE, 2024. |
| Publication Year: |
2024 |
| Document Type: |
Article |
| DOI: |
10.1109/icecsp61809.2024.10698316 |
| Rights: |
STM Policy #29 |
| Accession Number: |
edsair.doi...........e56f7ad5004ccfed83b59d66adc38ba1 |
| Database: |
OpenAIRE |