Chatterjee, A., Roy, R., & d'Abreu, M. (1993). Greedy hardware optimization for linear digital circuits using number splitting and refactorization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1(4), 423. https://doi.org/10.1109/92.250189
Παραπομπή σε μορφή Chicago (17η εκδ.)Chatterjee, A., R.K Roy, και M.A d'Abreu. "Greedy Hardware Optimization for Linear Digital Circuits Using Number Splitting and Refactorization." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1, no. 4 (1993): 423. https://doi.org/10.1109/92.250189.
Παραπομπή σε μορφή MLA (9th εκδ.)Chatterjee, A., et al. "Greedy Hardware Optimization for Linear Digital Circuits Using Number Splitting and Refactorization." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 1, no. 4, 1993, p. 423, https://doi.org/10.1109/92.250189.