Academic Journal
Processing while routing: a network-on-chip-based parallel system.
| Τίτλος: | Processing while routing: a network-on-chip-based parallel system. |
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| Συγγραφείς: | Fernandes, S. R., Oliveira, B. C., Costa, M., Silva, I. S. |
| Πηγή: | IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p525-538, 14p, 9 Diagrams, 2 Charts, 10 Graphs |
| Θεματικοί όροι: | Computer architecture, Network routers, Systems development, Computer input-output equipment, Computer systems |
| Περίληψη: | Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath. [ABSTRACT FROM AUTHOR] |
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| Βάση Δεδομένων: | Complementary Index |
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