Academic Journal
Processing while routing: a network-on-chip-based parallel system.
| Τίτλος: | Processing while routing: a network-on-chip-based parallel system. |
|---|---|
| Συγγραφείς: | Fernandes, S. R., Oliveira, B. C., Costa, M., Silva, I. S. |
| Πηγή: | IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p525-538, 14p, 9 Diagrams, 2 Charts, 10 Graphs |
| Θεματικοί όροι: | Computer architecture, Network routers, Systems development, Computer input-output equipment, Computer systems |
| Περίληψη: | Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath. [ABSTRACT FROM AUTHOR] |
| Copyright of IET Computers & Digital Techniques (Institution of Engineering & Technology) is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Βάση Δεδομένων: | Complementary Index |
| FullText | Text: Availability: 0 |
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| Header | DbId: edb DbLabel: Complementary Index An: 43594190 RelevancyScore: 833 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 833.491455078125 |
| IllustrationInfo | |
| Items | – Name: Title Label: Title Group: Ti Data: Processing while routing: a network-on-chip-based parallel system. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Fernandes%2C+S%2E+R%2E%22">Fernandes, S. R.</searchLink><br /><searchLink fieldCode="AR" term="%22Oliveira%2C+B%2E+C%2E%22">Oliveira, B. C.</searchLink><br /><searchLink fieldCode="AR" term="%22Costa%2C+M%2E%22">Costa, M.</searchLink><br /><searchLink fieldCode="AR" term="%22Silva%2C+I%2E+S%2E%22">Silva, I. S.</searchLink> – Name: TitleSource Label: Source Group: Src Data: IET Computers & Digital Techniques (Institution of Engineering & Technology); Sep2009, Vol. 3 Issue 5, p525-538, 14p, 9 Diagrams, 2 Charts, 10 Graphs – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Network+routers%22">Network routers</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+development%22">Systems development</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+input-output+equipment%22">Computer input-output equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+systems%22">Computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of IET Computers & Digital Techniques (Institution of Engineering & Technology) is the property of Institution of Engineering & Technology and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
| PLink | https://search.ebscohost.com/login.aspx?direct=true&site=eds-live&db=edb&AN=43594190 |
| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1049/iet-cdt.2008.0071 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 14 StartPage: 525 Subjects: – SubjectFull: Computer architecture Type: general – SubjectFull: Network routers Type: general – SubjectFull: Systems development Type: general – SubjectFull: Computer input-output equipment Type: general – SubjectFull: Computer systems Type: general Titles: – TitleFull: Processing while routing: a network-on-chip-based parallel system. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Fernandes, S. R. – PersonEntity: Name: NameFull: Oliveira, B. C. – PersonEntity: Name: NameFull: Costa, M. – PersonEntity: Name: NameFull: Silva, I. S. IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 09 Text: Sep2009 Type: published Y: 2009 Identifiers: – Type: issn-print Value: 17518601 Numbering: – Type: volume Value: 3 – Type: issue Value: 5 Titles: – TitleFull: IET Computers & Digital Techniques (Institution of Engineering & Technology) Type: main |
| ResultId | 1 |