Academic Journal
Systematic Software-Based Self-Test for Pipelined Processors.
| Title: | Systematic Software-Based Self-Test for Pipelined Processors. |
|---|---|
| Authors: | Gizopoulos, Dimitris, Psarakis, Mihalis, Hatzimihail, Miltiadis, Maniatakos, Michail, Paschalis, Antonis, Raghunathan, Anand, Ravi, Srivaths |
| Source: | IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Nov2008, Vol. 16 Issue 11, p1441-1453, 13p, 7 Black and White Photographs, 9 Diagrams, 6 Charts |
| Subject Terms: | Integrated circuits, Reduced instruction set computers, Data pipelining, Microprocessors, Automatic test equipment, Field programmable gate arrays, Memory maps (Computer science), XML (Extensible Markup Language), Computer architecture |
| Abstract: | Abstract-Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Complementary Index |
| FullText | Links: – Type: other Text: Availability: 0 |
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| Header | DbId: edb DbLabel: Complementary Index An: 35110074 RelevancyScore: 833 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 833.212341308594 |
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| Items | – Name: Title Label: Title Group: Ti Data: Systematic Software-Based Self-Test for Pipelined Processors. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Gizopoulos%2C+Dimitris%22">Gizopoulos, Dimitris</searchLink><br /><searchLink fieldCode="AR" term="%22Psarakis%2C+Mihalis%22">Psarakis, Mihalis</searchLink><br /><searchLink fieldCode="AR" term="%22Hatzimihail%2C+Miltiadis%22">Hatzimihail, Miltiadis</searchLink><br /><searchLink fieldCode="AR" term="%22Maniatakos%2C+Michail%22">Maniatakos, Michail</searchLink><br /><searchLink fieldCode="AR" term="%22Paschalis%2C+Antonis%22">Paschalis, Antonis</searchLink><br /><searchLink fieldCode="AR" term="%22Raghunathan%2C+Anand%22">Raghunathan, Anand</searchLink><br /><searchLink fieldCode="AR" term="%22Ravi%2C+Srivaths%22">Ravi, Srivaths</searchLink> – Name: TitleSource Label: Source Group: Src Data: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Nov2008, Vol. 16 Issue 11, p1441-1453, 13p, 7 Black and White Photographs, 9 Diagrams, 6 Charts – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Integrated+circuits%22">Integrated circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Reduced+instruction+set+computers%22">Reduced instruction set computers</searchLink><br /><searchLink fieldCode="DE" term="%22Data+pipelining%22">Data pipelining</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Automatic+test+equipment%22">Automatic test equipment</searchLink><br /><searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Memory+maps+%28Computer+science%29%22">Memory maps (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22XML+%28Extensible+Markup+Language%29%22">XML (Extensible Markup Language)</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Abstract-Software-based self-test (SBST) has recently emerged as an effective methodology for the manufacturing test of processors and other components in systems-on-chip (SoCs). By moving test related functions from external resources to the SoC's interior, in the form of test programs that the on-chip processor executes, SBST significantly reduces the need for high-cost, big-iron testers, and enables high-quality at-speed testing and performance binning. Thus far, SBST approaches have focused almost exclusively on the functional (programmer visible) components of the processor. In this paper, we analyze the challenges involved in testing an important component of modern processors, namely, the pipelining logic, and propose a systematic SBST methodology to address them. We first demonstrate that SBST programs that only target the functional components of the processor are not sufficient to test the pipeline logic, resulting in a significant loss of overall processor fault coverage. We further identify the testability hotspots in the pipeline logic using two fully pipelined reduced instruction set computer (RISC) processor benchmarks. Finally, we develop a systematic SBST methodology that enhances existing SBST programs so that they comprehensively test the pipeline logic. The proposed methodology is complementary to previous SBST techniques that target functional components (their results can form the input to our methodology, and thus we can reuse the test development effort behind preexisting SBST programs). We automate our methodology and incorporate it in an integrated software environment (developed using Java, XML, and archC) for the automatic generation of SBST routines for microprocessors. We apply the methodology to the two complex benchmark RISC processors with respect to two fault models: stuck-at fault model and transition delay fault model. Simulation results show that our methodology provides significant improvements for the two fault models, both for the entire processor (12% fault coverage improvement on average) and for the pipeline logic itself (19% fault coverage improvement on average), compared to a conventional SBST approach. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of IEEE Transactions on Very Large Scale Integration (VLSI) Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/TVLSI.2008.2000866 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 13 StartPage: 1441 Subjects: – SubjectFull: Integrated circuits Type: general – SubjectFull: Reduced instruction set computers Type: general – SubjectFull: Data pipelining Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Automatic test equipment Type: general – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Memory maps (Computer science) Type: general – SubjectFull: XML (Extensible Markup Language) Type: general – SubjectFull: Computer architecture Type: general Titles: – TitleFull: Systematic Software-Based Self-Test for Pipelined Processors. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Gizopoulos, Dimitris – PersonEntity: Name: NameFull: Psarakis, Mihalis – PersonEntity: Name: NameFull: Hatzimihail, Miltiadis – PersonEntity: Name: NameFull: Maniatakos, Michail – PersonEntity: Name: NameFull: Paschalis, Antonis – PersonEntity: Name: NameFull: Raghunathan, Anand – PersonEntity: Name: NameFull: Ravi, Srivaths IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 11 Text: Nov2008 Type: published Y: 2008 Identifiers: – Type: issn-print Value: 10638210 Numbering: – Type: volume Value: 16 – Type: issue Value: 11 Titles: – TitleFull: IEEE Transactions on Very Large Scale Integration (VLSI) Systems Type: main |
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