Academic Journal
Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs.
| Τίτλος: | Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs. |
|---|---|
| Συγγραφείς: | Wang, Shuo, Chen, Lei, Tian, Chunsheng, Zhou, Jing, Zhang, Yaowei, Cao, Yongzheng |
| Πηγή: | Electronics (2079-9292); Aug2026, Vol. 15 Issue 16, p3536, 51p |
| Θεματικοί όροι: | Deep learning, Programmable logic devices, Compilers (Computer programs), Run time systems (Computer science), Software architecture, Electronic design automation, Mathematical optimization |
| Περίληψη: | Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency. [ABSTRACT FROM AUTHOR] |
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| Βάση Δεδομένων: | Complementary Index |
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| Items | – Name: Title Label: Title Group: Ti Data: Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Wang%2C+Shuo%22">Wang, Shuo</searchLink><br /><searchLink fieldCode="AR" term="%22Chen%2C+Lei%22">Chen, Lei</searchLink><br /><searchLink fieldCode="AR" term="%22Tian%2C+Chunsheng%22">Tian, Chunsheng</searchLink><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Jing%22">Zhou, Jing</searchLink><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Yaowei%22">Zhang, Yaowei</searchLink><br /><searchLink fieldCode="AR" term="%22Cao%2C+Yongzheng%22">Cao, Yongzheng</searchLink> – Name: TitleSource Label: Source Group: Src Data: Electronics (2079-9292); Aug2026, Vol. 15 Issue 16, p3536, 51p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Deep+learning%22">Deep learning</searchLink><br /><searchLink fieldCode="DE" term="%22Programmable+logic+devices%22">Programmable logic devices</searchLink><br /><searchLink fieldCode="DE" term="%22Compilers+%28Computer+programs%29%22">Compilers (Computer programs)</searchLink><br /><searchLink fieldCode="DE" term="%22Run+time+systems+%28Computer+science%29%22">Run time systems (Computer science)</searchLink><br /><searchLink fieldCode="DE" term="%22Software+architecture%22">Software architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Electronic+design+automation%22">Electronic design automation</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+optimization%22">Mathematical optimization</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Deep learning (DL) models have achieved remarkable progress in natural language processing, computer vision, content generation, and edge intelligence; however, their rapidly increasing computational complexity, memory demand, and deployment diversity pose significant challenges for practical implementation. Field-programmable gate arrays (FPGAs) provide customized low-precision computation, spatial dataflow, on-chip data reuse, reconfigurability, and rich I/O capabilities, making them an important platform for DL inference. This paper presents a systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA). Following a PRISMA-guided evidence synthesis protocol, this review analyzes DL workload characteristics, FPGA architectural optimizations, deployment toolflows, and physical implementation challenges. A unified taxonomy is proposed along the specialization–programmability continuum, including model-fixed accelerators, generator-based accelerators, template-configurable accelerators, and ISA-programmable overlays. These approaches are compared according to hardware regeneration requirements, model adaptability, operator coverage, compilation cost, and deployment flexibility. Furthermore, emerging workloads, including vision Transformers, graph neural networks, large language models, and multimodal models, are analyzed from the perspectives of computation, memory behavior, and runtime coordination. The review shows that FPGA deployment efficiency increasingly depends on memory capacity, mutable state management, operator support, and end-to-end compilation capability rather than peak multiply–accumulate throughput alone. Based on the analysis of 70 primary FPGA implementation studies, this paper highlights that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch size, memory residency, FPGA platform, and evidence maturity. For multimodal generative models, the current evidence remains limited, with no identified end-to-end FPGA-based vision–language model implementation in the reviewed corpus. This review provides a systematic perspective for future FPGA-based DL deployment research, emphasizing cross-layer optimization, physically aware compilation, extensible accelerator architectures, and practical deployment efficiency. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of Electronics (2079-9292) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3390/electronics15163536 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 51 StartPage: 3536 Subjects: – SubjectFull: Deep learning Type: general – SubjectFull: Programmable logic devices Type: general – SubjectFull: Compilers (Computer programs) Type: general – SubjectFull: Run time systems (Computer science) Type: general – SubjectFull: Software architecture Type: general – SubjectFull: Electronic design automation Type: general – SubjectFull: Mathematical optimization Type: general Titles: – TitleFull: Analysis of Research Progress on Deployment Methods for Deep Learning Models on FPGAs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Wang, Shuo – PersonEntity: Name: NameFull: Chen, Lei – PersonEntity: Name: NameFull: Tian, Chunsheng – PersonEntity: Name: NameFull: Zhou, Jing – PersonEntity: Name: NameFull: Zhang, Yaowei – PersonEntity: Name: NameFull: Cao, Yongzheng IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 08 Text: Aug2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 20799292 Numbering: – Type: volume Value: 15 – Type: issue Value: 16 Titles: – TitleFull: Electronics (2079-9292) Type: main |
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