Academic Journal
Fine-Grained Structural Conflict Modeling for Compile-Time Instruction Scheduling on VLIW ASIPs.
| Τίτλος: | Fine-Grained Structural Conflict Modeling for Compile-Time Instruction Scheduling on VLIW ASIPs. |
|---|---|
| Συγγραφείς: | Hao, Peng, Zhang, Shengbing, Zhou, Xinbing, Man, Yi, Liu, Dake |
| Πηγή: | Electronics (2079-9292); Aug2026, Vol. 15 Issue 16, p3522, 23p |
| Θεματικοί όροι: | Resource management, Compilers (Computer programs), Microprocessors, Program transformation |
| Περίληψη: | Application-specific instruction set processors (ASIPs) often employ specialized hardware to improve performance, but this introduces complexity in resource management and programming. Existing compiler solutions, including LLVM's default schedulers, lack fine-grained structural conflict analysis for complex arithmetic logic unit (ALU) instructions, leading to suboptimal performance or runtime errors. This limitation becomes critical when targeting very long instruction word (VLIW) architectures with instruction fusion units that exhibit pipeline-stage-level resource contention. In this paper, we propose a compile-time instruction scheduling method that models sub-cycle resource usage and analyzes both data and structural dependencies at fine granularity. Unlike coarse-grained resource tables used in existing compilers, our approach tracks functional unit occupancy at the pipeline stage level, enabling precise detection of structural hazards in complex execution units. We implement this scheduler as a backend pass in the LLVM compiler framework and validate it on the Sayram VLIW processor for wireless communication. Experimental results show that our approach achieves 100% scheduling correctness while improving execution efficiency by 23% on average compared with in-order scheduling, with benefits up to 38% for highly parallel kernels such as PRACH, and reducing average running time by 66% compared with atomic execution. [ABSTRACT FROM AUTHOR] |
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| Βάση Δεδομένων: | Complementary Index |
| FullText | Text: Availability: 0 CustomLinks: – Url: https://resolver.ebsco.com/c/fiv2js/result?sid=EBSCO:edb&genre=article&issn=20799292&ISBN=&volume=15&issue=16&date=20260815&spage=3522&pages=3522-3544&title=Electronics (2079-9292)&atitle=Fine-Grained%20Structural%20Conflict%20Modeling%20for%20Compile-Time%20Instruction%20Scheduling%20on%20VLIW%20ASIPs.&aulast=Hao%2C%20Peng&id=DOI:10.3390/electronics15163522 Name: Full Text Finder (for New FTF UI) (ns324271) Category: fullText Text: Full Text Finder MouseOverText: Full Text Finder |
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| Items | – Name: Title Label: Title Group: Ti Data: Fine-Grained Structural Conflict Modeling for Compile-Time Instruction Scheduling on VLIW ASIPs. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Hao%2C+Peng%22">Hao, Peng</searchLink><br /><searchLink fieldCode="AR" term="%22Zhang%2C+Shengbing%22">Zhang, Shengbing</searchLink><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Xinbing%22">Zhou, Xinbing</searchLink><br /><searchLink fieldCode="AR" term="%22Man%2C+Yi%22">Man, Yi</searchLink><br /><searchLink fieldCode="AR" term="%22Liu%2C+Dake%22">Liu, Dake</searchLink> – Name: TitleSource Label: Source Group: Src Data: Electronics (2079-9292); Aug2026, Vol. 15 Issue 16, p3522, 23p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Resource+management%22">Resource management</searchLink><br /><searchLink fieldCode="DE" term="%22Compilers+%28Computer+programs%29%22">Compilers (Computer programs)</searchLink><br /><searchLink fieldCode="DE" term="%22Microprocessors%22">Microprocessors</searchLink><br /><searchLink fieldCode="DE" term="%22Program+transformation%22">Program transformation</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Application-specific instruction set processors (ASIPs) often employ specialized hardware to improve performance, but this introduces complexity in resource management and programming. Existing compiler solutions, including LLVM's default schedulers, lack fine-grained structural conflict analysis for complex arithmetic logic unit (ALU) instructions, leading to suboptimal performance or runtime errors. This limitation becomes critical when targeting very long instruction word (VLIW) architectures with instruction fusion units that exhibit pipeline-stage-level resource contention. In this paper, we propose a compile-time instruction scheduling method that models sub-cycle resource usage and analyzes both data and structural dependencies at fine granularity. Unlike coarse-grained resource tables used in existing compilers, our approach tracks functional unit occupancy at the pipeline stage level, enabling precise detection of structural hazards in complex execution units. We implement this scheduler as a backend pass in the LLVM compiler framework and validate it on the Sayram VLIW processor for wireless communication. Experimental results show that our approach achieves 100% scheduling correctness while improving execution efficiency by 23% on average compared with in-order scheduling, with benefits up to 38% for highly parallel kernels such as PRACH, and reducing average running time by 66% compared with atomic execution. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of Electronics (2079-9292) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3390/electronics15163522 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 23 StartPage: 3522 Subjects: – SubjectFull: Resource management Type: general – SubjectFull: Compilers (Computer programs) Type: general – SubjectFull: Microprocessors Type: general – SubjectFull: Program transformation Type: general Titles: – TitleFull: Fine-Grained Structural Conflict Modeling for Compile-Time Instruction Scheduling on VLIW ASIPs. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Hao, Peng – PersonEntity: Name: NameFull: Zhang, Shengbing – PersonEntity: Name: NameFull: Zhou, Xinbing – PersonEntity: Name: NameFull: Man, Yi – PersonEntity: Name: NameFull: Liu, Dake IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 08 Text: Aug2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 20799292 Numbering: – Type: volume Value: 15 – Type: issue Value: 16 Titles: – TitleFull: Electronics (2079-9292) Type: main |
| ResultId | 1 |