Academic Journal
A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout.
| Τίτλος: | A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout. |
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| Συγγραφείς: | Zhan, Aoming, Zhao, Ye, Zhou, Yumei, Qiao, Shushan |
| Πηγή: | Applied Sciences (2076-3417); Aug2026, Vol. 16 Issue 16, p8189, 19p |
| Θεματικοί όροι: | Time-digital conversion, Hardware design & construction, Artificial neural networks, Computer systems |
| Περίληψη: | Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection and time-domain accumulation. The proposed accelerator processes a 3 × 3 × 16 window for 16 output channels with 6-bit weights and activations. Each 6-bit minimum is divided into two 3-bit slices. A dual-mode digital-to-time converter (DM-DTC) encodes the most-significant slice in high-linearity (HL) mode and the least-significant slice in low-power (LP) mode. Readout is performed by a shared-clock time-to-digital converter (SC-TDC), in which one Gray-code time reference serves all paths while local latches preserve independent channel results. The training model reproduces code-dependent DTC nonlinearity, process–voltage–temperature variation, jitter, channel offset, TDC quantization, saturation, and scale mismatch. The architecture thereby combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation. Post-layout simulations in 55 nm show that the 0.359 mm2, 13.7 Kb design operates at 0.7–1.2 V and 5–30 MHz, consumes 0.025–0.324 mW, and achieves 43.2–94.3 TOPS/W. The normalized figure of merit is 6.01–13.09 POPS/W·bit2. On CIFAR-10/ResNet-20, hardware errors reduce the baseline accuracy from 92.71% to 86.26%; error-aware training achieves 91.53%. [ABSTRACT FROM AUTHOR] |
| Copyright of Applied Sciences (2076-3417) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Βάση Δεδομένων: | Complementary Index |
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| Header | DbId: edb DbLabel: Complementary Index An: 196617764 RelevancyScore: 1082 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 1082.42504882813 |
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| Items | – Name: Title Label: Title Group: Ti Data: A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Zhan%2C+Aoming%22">Zhan, Aoming</searchLink><br /><searchLink fieldCode="AR" term="%22Zhao%2C+Ye%22">Zhao, Ye</searchLink><br /><searchLink fieldCode="AR" term="%22Zhou%2C+Yumei%22">Zhou, Yumei</searchLink><br /><searchLink fieldCode="AR" term="%22Qiao%2C+Shushan%22">Qiao, Shushan</searchLink> – Name: TitleSource Label: Source Group: Src Data: Applied Sciences (2076-3417); Aug2026, Vol. 16 Issue 16, p8189, 19p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Time-digital+conversion%22">Time-digital conversion</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware+design+%26+construction%22">Hardware design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Artificial+neural+networks%22">Artificial neural networks</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+systems%22">Computer systems</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Adder neural networks remove multiplication from convolution, yet their direct L1-distance datapath still requires subtraction, absolute-value generation, and wide accumulation. We address this cost by mapping the online L1 operation to minimum selection and time-domain accumulation. The proposed accelerator processes a 3 × 3 × 16 window for 16 output channels with 6-bit weights and activations. Each 6-bit minimum is divided into two 3-bit slices. A dual-mode digital-to-time converter (DM-DTC) encodes the most-significant slice in high-linearity (HL) mode and the least-significant slice in low-power (LP) mode. Readout is performed by a shared-clock time-to-digital converter (SC-TDC), in which one Gray-code time reference serves all paths while local latches preserve independent channel results. The training model reproduces code-dependent DTC nonlinearity, process–voltage–temperature variation, jitter, channel offset, TDC quantization, saturation, and scale mismatch. The architecture thereby combines significance-aware time encoding, channel-scalable readout, and hardware-aware adaptation. Post-layout simulations in 55 nm show that the 0.359 mm<superscript>2</superscript>, 13.7 Kb design operates at 0.7–1.2 V and 5–30 MHz, consumes 0.025–0.324 mW, and achieves 43.2–94.3 TOPS/W. The normalized figure of merit is 6.01–13.09 POPS/W·bit<superscript>2</superscript>. On CIFAR-10/ResNet-20, hardware errors reduce the baseline accuracy from 92.71% to 86.26%; error-aware training achieves 91.53%. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of Applied Sciences (2076-3417) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3390/app16168189 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 19 StartPage: 8189 Subjects: – SubjectFull: Time-digital conversion Type: general – SubjectFull: Hardware design & construction Type: general – SubjectFull: Artificial neural networks Type: general – SubjectFull: Computer systems Type: general Titles: – TitleFull: A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Zhan, Aoming – PersonEntity: Name: NameFull: Zhao, Ye – PersonEntity: Name: NameFull: Zhou, Yumei – PersonEntity: Name: NameFull: Qiao, Shushan IsPartOfRelationships: – BibEntity: Dates: – D: 15 M: 08 Text: Aug2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 20763417 Numbering: – Type: volume Value: 16 – Type: issue Value: 16 Titles: – TitleFull: Applied Sciences (2076-3417) Type: main |
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