Zhan, A., Zhao, Y., Zhou, Y., & Qiao, S. (2026). A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout. Applied Sciences (2076-3417), 16(16), 8189-8207. https://doi.org/10.3390/app16168189
Παραπομπή σε μορφή Chicago (17η εκδ.)Zhan, Aoming, Ye Zhao, Yumei Zhou, και Shushan Qiao. "A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout." Applied Sciences (2076-3417) 16, no. 16 (2026): 8189-8207. https://doi.org/10.3390/app16168189.
Παραπομπή σε μορφή MLA (9th εκδ.)Zhan, Aoming, et al. "A Hardware-Error-Aware Time-Domain CIM Accelerator for AdderNet with Significance-Aware Dual-Mode DTC Encoding and Shared-Clock TDC Readout." Applied Sciences (2076-3417), vol. 16, no. 16, 2026, pp. 8189-8207, https://doi.org/10.3390/app16168189.