Academic Journal
Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets.
| Title: | Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets. |
|---|---|
| Authors: | Kopczynski, Maciej |
| Source: | International Journal of Electronics & Telecommunications; 2026, Vol. 72 Issue 3, p1-7, 7p |
| Subject Terms: | Field programmable gate arrays, Rough sets, Parallel programming, Big data, Computer architecture, Data reduction, Benchmark problems (Computer science) |
| Abstract: | Rough set theory, originally proposed by Z. Pawlak, constitutes an important framework for data analysis and processing in intelligent systems. As contemporary computational environments generate increasingly large datasets, the efficiency of data processing has become a central concern. Data reduction represents a key mechanism for improving computational performance. In the context of rough sets, such reduction is achieved through the elimination of redundant information using reducts. Existing reduct-generation algorithms are predominantly software-based, which entails several inherent limitations, including fixed word-length constraints and overhead associated with instruction fetching and data manipulation. These factors contribute to comparatively low execution performance. Hardware-oriented approaches offer substantially higher processing throughput. This study introduces an FPGA-based hardware solution incorporating a softcore CPU, designed for parallel computation of reducts in large datasets. The proposed solution was evaluated on two real-world datasets executed directly within the FPGA environment, with dataset sizes ranging from 1 000 to 1 000 000 objects. For benchmarking purposes, a corresponding implementation in C was executed on a standard PC. Processing times for both hardware and software variants were recorded and analyzed. [ABSTRACT FROM AUTHOR] |
| Copyright of International Journal of Electronics & Telecommunications is the property of Polish Academy of Sciences and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Database: | Complementary Index |
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| Items | – Name: Title Label: Title Group: Ti Data: Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Kopczynski%2C+Maciej%22">Kopczynski, Maciej</searchLink> – Name: TitleSource Label: Source Group: Src Data: International Journal of Electronics & Telecommunications; 2026, Vol. 72 Issue 3, p1-7, 7p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Field+programmable+gate+arrays%22">Field programmable gate arrays</searchLink><br /><searchLink fieldCode="DE" term="%22Rough+sets%22">Rough sets</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+programming%22">Parallel programming</searchLink><br /><searchLink fieldCode="DE" term="%22Big+data%22">Big data</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+architecture%22">Computer architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Data+reduction%22">Data reduction</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+problems+%28Computer+science%29%22">Benchmark problems (Computer science)</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Rough set theory, originally proposed by Z. Pawlak, constitutes an important framework for data analysis and processing in intelligent systems. As contemporary computational environments generate increasingly large datasets, the efficiency of data processing has become a central concern. Data reduction represents a key mechanism for improving computational performance. In the context of rough sets, such reduction is achieved through the elimination of redundant information using reducts. Existing reduct-generation algorithms are predominantly software-based, which entails several inherent limitations, including fixed word-length constraints and overhead associated with instruction fetching and data manipulation. These factors contribute to comparatively low execution performance. Hardware-oriented approaches offer substantially higher processing throughput. This study introduces an FPGA-based hardware solution incorporating a softcore CPU, designed for parallel computation of reducts in large datasets. The proposed solution was evaluated on two real-world datasets executed directly within the FPGA environment, with dataset sizes ranging from 1 000 to 1 000 000 objects. For benchmarking purposes, a corresponding implementation in C was executed on a standard PC. Processing times for both hardware and software variants were recorded and analyzed. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of International Journal of Electronics & Telecommunications is the property of Polish Academy of Sciences and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.24425/ijet.2026.1721 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 7 StartPage: 1 Subjects: – SubjectFull: Field programmable gate arrays Type: general – SubjectFull: Rough sets Type: general – SubjectFull: Parallel programming Type: general – SubjectFull: Big data Type: general – SubjectFull: Computer architecture Type: general – SubjectFull: Data reduction Type: general – SubjectFull: Benchmark problems (Computer science) Type: general Titles: – TitleFull: Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Kopczynski, Maciej IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: 2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 20818491 Numbering: – Type: volume Value: 72 – Type: issue Value: 3 Titles: – TitleFull: International Journal of Electronics & Telecommunications Type: main |
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