Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets. |
| Συγγραφείς: |
Kopczynski, Maciej |
| Πηγή: |
International Journal of Electronics & Telecommunications; 2026, Vol. 72 Issue 3, p1-7, 7p |
| Θεματικοί όροι: |
Field programmable gate arrays, Rough sets, Parallel programming, Big data, Computer architecture, Data reduction, Benchmark problems (Computer science) |
| Περίληψη: |
Rough set theory, originally proposed by Z. Pawlak, constitutes an important framework for data analysis and processing in intelligent systems. As contemporary computational environments generate increasingly large datasets, the efficiency of data processing has become a central concern. Data reduction represents a key mechanism for improving computational performance. In the context of rough sets, such reduction is achieved through the elimination of redundant information using reducts. Existing reduct-generation algorithms are predominantly software-based, which entails several inherent limitations, including fixed word-length constraints and overhead associated with instruction fetching and data manipulation. These factors contribute to comparatively low execution performance. Hardware-oriented approaches offer substantially higher processing throughput. This study introduces an FPGA-based hardware solution incorporating a softcore CPU, designed for parallel computation of reducts in large datasets. The proposed solution was evaluated on two real-world datasets executed directly within the FPGA environment, with dataset sizes ranging from 1 000 to 1 000 000 objects. For benchmarking purposes, a corresponding implementation in C was executed on a standard PC. Processing times for both hardware and software variants were recorded and analyzed. [ABSTRACT FROM AUTHOR] |
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| Βάση Δεδομένων: |
Complementary Index |