Kopczynski, M. (2026). Scalable FPGA hardware architecture for parallel reduct computation in big datasets Using rough sets. International Journal of Electronics & Telecommunications, 72(3), 1-7. https://doi.org/10.24425/ijet.2026.1721
Παραπομπή σε μορφή Chicago (17η εκδ.)Kopczynski, Maciej. "Scalable FPGA Hardware Architecture for Parallel Reduct Computation in Big Datasets Using Rough Sets." International Journal of Electronics & Telecommunications 72, no. 3 (2026): 1-7. https://doi.org/10.24425/ijet.2026.1721.
Παραπομπή σε μορφή MLA (9th εκδ.)Kopczynski, Maciej. "Scalable FPGA Hardware Architecture for Parallel Reduct Computation in Big Datasets Using Rough Sets." International Journal of Electronics & Telecommunications, vol. 72, no. 3, 2026, pp. 1-7, https://doi.org/10.24425/ijet.2026.1721.