A Novel High-Frequency Simulation Methodology for IBIS Models Utilizing Verilog-AMS Dynamic Parameter Compensation.

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Τίτλος:	A Novel High-Frequency Simulation Methodology for IBIS Models Utilizing Verilog-AMS Dynamic Parameter Compensation.
Συγγραφείς:	Xu, Yihui, Dong, Yuan, Chen, Jiahang, Jiang, Xiaoqing, Ning, Yafei
Πηγή:	Electronics (2079-9292); Jul2026, Vol. 15 Issue 13, p2906, 21p
Θεματικοί όροι:	Signal integrity (Electronics), Simulation Program with Integrated Circuit Emphasis, Computer hardware description languages, Computer simulation, Transient analysis
Περίληψη:	Conventional I/O Buffer Information Specification (IBIS) models often suffer from reduced fidelity in high-speed signaling because their static table-lookup mechanism cannot accurately reproduce complex transient I/O-buffer dynamics. To address this limitation, this study proposes a Verilog-AMS-based dynamic parameter compensation method. First, the conventional IBIS model is reformulated into a three-layer architecture comprising a data interface layer, an intermediate variable computation layer, and a port response synthesis layer. Then, based on Kirchhoff's current law (KCL), the monotonic dependence of the output voltage on the pull-up and pull-down driving factors, kpu and kpd, is analytically derived to provide a directional criterion for parameter correction. Building on this criterion, a pulse-width-driven compensation algorithm is developed by constructing a pulse-width-indexed dual-factor empirical adjustment matrix and detecting the pulse width of the input bitstream in real time during transient simulation. The detected pulse width is then used to dynamically update kpu and kpd, enabling the IBIS response to converge toward the transistor-level SPICE reference waveform. Three representative device models were evaluated at 666 Mbps and 1.302 Gbps using pseudo-random binary sequence excitation, and the model fidelity was quantified using the normalized mean square error (NMSE). The proposed method reduced the NMSE from −6.73 to −1.03 dB before compensation to −54.79 to −44.19 dB after compensation, demonstrating a substantial improvement in high-frequency IBIS modeling fidelity and confirming the robustness and adaptability of the pulse-width-aware dynamic compensation strategy under random high-speed excitation. [ABSTRACT FROM AUTHOR]
	Copyright of Electronics (2079-9292) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
Βάση Δεδομένων:	Complementary Index

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Items	– Name: Title Label: Title Group: Ti Data: A Novel High-Frequency Simulation Methodology for IBIS Models Utilizing Verilog-AMS Dynamic Parameter Compensation. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Xu%2C+Yihui%22">Xu, Yihui</searchLink><br /><searchLink fieldCode="AR" term="%22Dong%2C+Yuan%22">Dong, Yuan</searchLink><br /><searchLink fieldCode="AR" term="%22Chen%2C+Jiahang%22">Chen, Jiahang</searchLink><br /><searchLink fieldCode="AR" term="%22Jiang%2C+Xiaoqing%22">Jiang, Xiaoqing</searchLink><br /><searchLink fieldCode="AR" term="%22Ning%2C+Yafei%22">Ning, Yafei</searchLink> – Name: TitleSource Label: Source Group: Src Data: Electronics (2079-9292); Jul2026, Vol. 15 Issue 13, p2906, 21p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Signal+integrity+%28Electronics%29%22">Signal integrity (Electronics)</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+Program+with+Integrated+Circuit+Emphasis%22">Simulation Program with Integrated Circuit Emphasis</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+hardware+description+languages%22">Computer hardware description languages</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Transient+analysis%22">Transient analysis</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: Conventional I/O Buffer Information Specification (IBIS) models often suffer from reduced fidelity in high-speed signaling because their static table-lookup mechanism cannot accurately reproduce complex transient I/O-buffer dynamics. To address this limitation, this study proposes a Verilog-AMS-based dynamic parameter compensation method. First, the conventional IBIS model is reformulated into a three-layer architecture comprising a data interface layer, an intermediate variable computation layer, and a port response synthesis layer. Then, based on Kirchhoff's current law (KCL), the monotonic dependence of the output voltage on the pull-up and pull-down driving factors, k<subscript>pu</subscript> and k<subscript>pd</subscript>, is analytically derived to provide a directional criterion for parameter correction. Building on this criterion, a pulse-width-driven compensation algorithm is developed by constructing a pulse-width-indexed dual-factor empirical adjustment matrix and detecting the pulse width of the input bitstream in real time during transient simulation. The detected pulse width is then used to dynamically update k<subscript>pu</subscript> and k<subscript>pd</subscript>, enabling the IBIS response to converge toward the transistor-level SPICE reference waveform. Three representative device models were evaluated at 666 Mbps and 1.302 Gbps using pseudo-random binary sequence excitation, and the model fidelity was quantified using the normalized mean square error (NMSE). The proposed method reduced the NMSE from −6.73 to −1.03 dB before compensation to −54.79 to −44.19 dB after compensation, demonstrating a substantial improvement in high-frequency IBIS modeling fidelity and confirming the robustness and adaptability of the pulse-width-aware dynamic compensation strategy under random high-speed excitation. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of Electronics (2079-9292) is the property of MDPI and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo	BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.3390/electronics15132906 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 21 StartPage: 2906 Subjects: – SubjectFull: Signal integrity (Electronics) Type: general – SubjectFull: Simulation Program with Integrated Circuit Emphasis Type: general – SubjectFull: Computer hardware description languages Type: general – SubjectFull: Computer simulation Type: general – SubjectFull: Transient analysis Type: general Titles: – TitleFull: A Novel High-Frequency Simulation Methodology for IBIS Models Utilizing Verilog-AMS Dynamic Parameter Compensation. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Xu, Yihui – PersonEntity: Name: NameFull: Dong, Yuan – PersonEntity: Name: NameFull: Chen, Jiahang – PersonEntity: Name: NameFull: Jiang, Xiaoqing – PersonEntity: Name: NameFull: Ning, Yafei IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 20799292 Numbering: – Type: volume Value: 15 – Type: issue Value: 13 Titles: – TitleFull: Electronics (2079-9292) Type: main
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