Academic Journal
Design of 18-Bit Resolution CT Delta-Sigma ADCs Using Single-Ended DAC with Mixed-Signal Calibration and OTA With Optimized Transconductance to Drain Current Ratio.
| Τίτλος: | Design of 18-Bit Resolution CT Delta-Sigma ADCs Using Single-Ended DAC with Mixed-Signal Calibration and OTA With Optimized Transconductance to Drain Current Ratio. |
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| Συγγραφείς: | Shailaja, J., Ravindran, Ernest |
| Πηγή: | Circuits, Systems & Signal Processing; Jul2026, Vol. 45 Issue 7, p5163-5190, 28p |
| Θεματικοί όροι: | Delta-sigma modulation, Digital-to-analog converters, Analog-to-digital converters, Comparator circuits, Simulation Program with Integrated Circuit Emphasis, Signal-to-noise ratio, Calibration |
| Περίληψη: | This study proposes a new continuous-time delta-sigma modulator (CT∆ΣM) that uses an operational transconductance amplifier (OTA) with an optimized transconductance and a single-ended digital-to-analog converter (DAC) with mixed-signal calibration (MSC) to drain current ratio. The CT∆ΣM comprises loop filters, successive-approximation register (SAR) quantizer, and DAC modules. An effective OTA-based input integrator is necessary since the loop filter has been used as a cascade of integrators. Further, the transconductance is used for executing the CNTFET based OTA to measure the drain current ratio. The CT∆ΣM uses a virtual-ground-switched resistive DAC at the feedback path to minimize power and distortion. An identification of a single-ended DAC equivalent has been made in order to improve the analysis. The Component mismatches and nonlinearities introduced by DAC units are reduced using a mixed-signal calibration scheme. In addition, the proposed CT∆ΣM reduces the feedback loop by using successive-approximation register analog to digital converter (SAR ADC) quantizer. After that, a new CNTFET comparator with a robust arm structure is used to balance speed and power consumption. The Cadence Virtuoso tool is used to simulate the proposed model and the performance metrics are evaluated to determine the model's ability to reduce the current ratio. Thus, the proposed model achieves a higher signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), etc., and the obtained results outperform the performance of the current models. [ABSTRACT FROM AUTHOR] |
| Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Βάση Δεδομένων: | Complementary Index |
| FullText | Links: – Type: other Text: Availability: 0 CustomLinks: – Url: https://dx.doi.org/doi:10.1007/s00034-025-03461-7 Name: EDS - Springer Nature Journals (s7799221) Category: fullText Text: View record at Springer |
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| Header | DbId: edb DbLabel: Complementary Index An: 194867719 RelevancyScore: 1082 AccessLevel: 6 PubType: Academic Journal PubTypeId: academicJournal PreciseRelevancyScore: 1082.42175292969 |
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| Items | – Name: Title Label: Title Group: Ti Data: Design of 18-Bit Resolution CT Delta-Sigma ADCs Using Single-Ended DAC with Mixed-Signal Calibration and OTA With Optimized Transconductance to Drain Current Ratio. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Shailaja%2C+J%2E%22">Shailaja, J.</searchLink><br /><searchLink fieldCode="AR" term="%22Ravindran%2C+Ernest%22">Ravindran, Ernest</searchLink> – Name: TitleSource Label: Source Group: Src Data: Circuits, Systems & Signal Processing; Jul2026, Vol. 45 Issue 7, p5163-5190, 28p – Name: Subject Label: Subject Terms Group: Su Data: <searchLink fieldCode="DE" term="%22Delta-sigma+modulation%22">Delta-sigma modulation</searchLink><br /><searchLink fieldCode="DE" term="%22Digital-to-analog+converters%22">Digital-to-analog converters</searchLink><br /><searchLink fieldCode="DE" term="%22Analog-to-digital+converters%22">Analog-to-digital converters</searchLink><br /><searchLink fieldCode="DE" term="%22Comparator+circuits%22">Comparator circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Simulation+Program+with+Integrated+Circuit+Emphasis%22">Simulation Program with Integrated Circuit Emphasis</searchLink><br /><searchLink fieldCode="DE" term="%22Signal-to-noise+ratio%22">Signal-to-noise ratio</searchLink><br /><searchLink fieldCode="DE" term="%22Calibration%22">Calibration</searchLink> – Name: Abstract Label: Abstract Group: Ab Data: This study proposes a new continuous-time delta-sigma modulator (CT∆ΣM) that uses an operational transconductance amplifier (OTA) with an optimized transconductance and a single-ended digital-to-analog converter (DAC) with mixed-signal calibration (MSC) to drain current ratio. The CT∆ΣM comprises loop filters, successive-approximation register (SAR) quantizer, and DAC modules. An effective OTA-based input integrator is necessary since the loop filter has been used as a cascade of integrators. Further, the transconductance is used for executing the CNTFET based OTA to measure the drain current ratio. The CT∆ΣM uses a virtual-ground-switched resistive DAC at the feedback path to minimize power and distortion. An identification of a single-ended DAC equivalent has been made in order to improve the analysis. The Component mismatches and nonlinearities introduced by DAC units are reduced using a mixed-signal calibration scheme. In addition, the proposed CT∆ΣM reduces the feedback loop by using successive-approximation register analog to digital converter (SAR ADC) quantizer. After that, a new CNTFET comparator with a robust arm structure is used to balance speed and power consumption. The Cadence Virtuoso tool is used to simulate the proposed model and the performance metrics are evaluated to determine the model's ability to reduce the current ratio. Thus, the proposed model achieves a higher signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SNDR), etc., and the obtained results outperform the performance of the current models. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of Circuits, Systems & Signal Processing is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1007/s00034-025-03461-7 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 28 StartPage: 5163 Subjects: – SubjectFull: Delta-sigma modulation Type: general – SubjectFull: Digital-to-analog converters Type: general – SubjectFull: Analog-to-digital converters Type: general – SubjectFull: Comparator circuits Type: general – SubjectFull: Simulation Program with Integrated Circuit Emphasis Type: general – SubjectFull: Signal-to-noise ratio Type: general – SubjectFull: Calibration Type: general Titles: – TitleFull: Design of 18-Bit Resolution CT Delta-Sigma ADCs Using Single-Ended DAC with Mixed-Signal Calibration and OTA With Optimized Transconductance to Drain Current Ratio. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Shailaja, J. – PersonEntity: Name: NameFull: Ravindran, Ernest IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 07 Text: Jul2026 Type: published Y: 2026 Identifiers: – Type: issn-print Value: 0278081X Numbering: – Type: volume Value: 45 – Type: issue Value: 7 Titles: – TitleFull: Circuits, Systems & Signal Processing Type: main |
| ResultId | 1 |