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Stacking technique for less power consumption in CMOS VLSI circuits.

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Title: Stacking technique for less power consumption in CMOS VLSI circuits.
Authors: Shivaprasad, Doma, Sarma, Anand, Kumar, Sai, Nikhil, Chinnala, Ganesan, Packyanathan, Raju, Vegesina Vijaya Rama, Chikine, Sridhar Babu, Husain, Saif O.
Source: AIP Conference Proceedings; 2025, Vol. 3361 Issue 1, p1-5, 5p
Subject Terms: Electric power consumption, Complementary metal oxide semiconductors, Power resources management, Computer simulation, Very large scale circuit integration, Energy conservation, Digital electronics
Abstract: For the reduction of power consumption in CMOS VLSI circuits—we have a stacking technique that is built-in feature of CMOS technology, By logic gate inactivity we reduce the power consumption in CMOS. Comprehensive study shows that the strategy reduces power more effectively than normal approaches. When applied to different digital circuits, such as half adders, Full adders good outcomes are obtained we confirm these outcomes by simulation. This method solves a major solves the power consumption in VLSI. Future researchers are going to do further implementation for the digital circuits to explore its into the low power systems. The researchers will provide the platform for the low power VLSI Design. This will encourage into additional discoveries and advancements into the VLSI field. [ABSTRACT FROM AUTHOR]
Copyright of AIP Conference Proceedings is the property of American Institute of Physics and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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DbLabel: Complementary Index
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PubType: Conference
PubTypeId: conference
PreciseRelevancyScore: 1038.09350585938
IllustrationInfo
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  Label: Title
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  Data: Stacking technique for less power consumption in CMOS VLSI circuits.
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  Data: <searchLink fieldCode="AR" term="%22Shivaprasad%2C+Doma%22">Shivaprasad, Doma</searchLink><br /><searchLink fieldCode="AR" term="%22Sarma%2C+Anand%22">Sarma, Anand</searchLink><br /><searchLink fieldCode="AR" term="%22Kumar%2C+Sai%22">Kumar, Sai</searchLink><br /><searchLink fieldCode="AR" term="%22Nikhil%2C+Chinnala%22">Nikhil, Chinnala</searchLink><br /><searchLink fieldCode="AR" term="%22Ganesan%2C+Packyanathan%22">Ganesan, Packyanathan</searchLink><br /><searchLink fieldCode="AR" term="%22Raju%2C+Vegesina+Vijaya+Rama%22">Raju, Vegesina Vijaya Rama</searchLink><br /><searchLink fieldCode="AR" term="%22Chikine%2C+Sridhar+Babu%22">Chikine, Sridhar Babu</searchLink><br /><searchLink fieldCode="AR" term="%22Husain%2C+Saif+O%2E%22">Husain, Saif O.</searchLink>
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  Data: AIP Conference Proceedings; 2025, Vol. 3361 Issue 1, p1-5, 5p
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  Data: <searchLink fieldCode="DE" term="%22Electric+power+consumption%22">Electric power consumption</searchLink><br /><searchLink fieldCode="DE" term="%22Complementary+metal+oxide+semiconductors%22">Complementary metal oxide semiconductors</searchLink><br /><searchLink fieldCode="DE" term="%22Power+resources+management%22">Power resources management</searchLink><br /><searchLink fieldCode="DE" term="%22Computer+simulation%22">Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Very+large+scale+circuit+integration%22">Very large scale circuit integration</searchLink><br /><searchLink fieldCode="DE" term="%22Energy+conservation%22">Energy conservation</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink>
– Name: Abstract
  Label: Abstract
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  Data: For the reduction of power consumption in CMOS VLSI circuits—we have a stacking technique that is built-in feature of CMOS technology, By logic gate inactivity we reduce the power consumption in CMOS. Comprehensive study shows that the strategy reduces power more effectively than normal approaches. When applied to different digital circuits, such as half adders, Full adders good outcomes are obtained we confirm these outcomes by simulation. This method solves a major solves the power consumption in VLSI. Future researchers are going to do further implementation for the digital circuits to explore its into the low power systems. The researchers will provide the platform for the low power VLSI Design. This will encourage into additional discoveries and advancements into the VLSI field. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of AIP Conference Proceedings is the property of American Institute of Physics and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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    Identifiers:
      – Type: doi
        Value: 10.1063/5.0298531
    Languages:
      – Code: eng
        Text: English
    PhysicalDescription:
      Pagination:
        PageCount: 5
        StartPage: 1
    Subjects:
      – SubjectFull: Electric power consumption
        Type: general
      – SubjectFull: Complementary metal oxide semiconductors
        Type: general
      – SubjectFull: Power resources management
        Type: general
      – SubjectFull: Computer simulation
        Type: general
      – SubjectFull: Very large scale circuit integration
        Type: general
      – SubjectFull: Energy conservation
        Type: general
      – SubjectFull: Digital electronics
        Type: general
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      – TitleFull: Stacking technique for less power consumption in CMOS VLSI circuits.
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            NameFull: Shivaprasad, Doma
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            NameFull: Sarma, Anand
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            NameFull: Kumar, Sai
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            NameFull: Nikhil, Chinnala
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            NameFull: Ganesan, Packyanathan
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            NameFull: Raju, Vegesina Vijaya Rama
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            NameFull: Chikine, Sridhar Babu
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            NameFull: Husain, Saif O.
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              Text: 2025
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              Y: 2025
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              Value: 3361
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