Λεπτομέρειες βιβλιογραφικής εγγραφής
| Τίτλος: |
Stacking technique for less power consumption in CMOS VLSI circuits. |
| Συγγραφείς: |
Shivaprasad, Doma, Sarma, Anand, Kumar, Sai, Nikhil, Chinnala, Ganesan, Packyanathan, Raju, Vegesina Vijaya Rama, Chikine, Sridhar Babu, Husain, Saif O. |
| Πηγή: |
AIP Conference Proceedings; 2025, Vol. 3361 Issue 1, p1-5, 5p |
| Θεματικοί όροι: |
Electric power consumption, Complementary metal oxide semiconductors, Power resources management, Computer simulation, Very large scale circuit integration, Energy conservation, Digital electronics |
| Περίληψη: |
For the reduction of power consumption in CMOS VLSI circuits—we have a stacking technique that is built-in feature of CMOS technology, By logic gate inactivity we reduce the power consumption in CMOS. Comprehensive study shows that the strategy reduces power more effectively than normal approaches. When applied to different digital circuits, such as half adders, Full adders good outcomes are obtained we confirm these outcomes by simulation. This method solves a major solves the power consumption in VLSI. Future researchers are going to do further implementation for the digital circuits to explore its into the low power systems. The researchers will provide the platform for the low power VLSI Design. This will encourage into additional discoveries and advancements into the VLSI field. [ABSTRACT FROM AUTHOR] |
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| Βάση Δεδομένων: |
Complementary Index |