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Algorithm profiling for architectures with dataflow accelerators.

Bibliographic Details
Title: Algorithm profiling for architectures with dataflow accelerators.
Authors: Korolija, Nenad, Milutinović, Veljko, Furht, Borko
Source: Journal of Big Data; 7/26/2025, Vol. 12 Issue 1, p1-31, 31p
Subject Terms: Data flow computing, High performance computing, Big data, Parallel processing, Instruction set architecture, Benchmark problems (Computer science)
Abstract: Dataflow computing has proved to be more efficient for certain high-performance computing algorithms. The prerequisites are that there is enough parallel calculation to cover the overhead of executing instructions on the dataflow hardware until the first result is ready. This is often true with algorithms that work with big data and that can process multiple iterations independently, e.g., while simulating certain phenomena in many elementary volumes. However, dataflow hardware runs typically at an order of magnitude lower frequencies compared to the control-flow processor. From a programmer's point of view, programming dataflow architectures is considerably harder than programming control-flow architectures. As a result, it is not always obvious whether programming dataflow architectures for certain algorithms is worth the effort needed. Therefore, there is a need for a programmer to be able to predict the outcome of programming for dataflow architectures in terms of accelerating program execution and power savings. This article presents a newly developed tool that a programmer can use for profiling control-flow algorithms and estimating the acceleration possibilities using the dataflow hardware. [ABSTRACT FROM AUTHOR]
Copyright of Journal of Big Data is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  – Url: https://dx.doi.org/doi:10.1186/s40537-025-01089-7
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  Data: Algorithm profiling for architectures with dataflow accelerators.
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  Data: <searchLink fieldCode="AR" term="%22Korolija%2C+Nenad%22">Korolija, Nenad</searchLink><br /><searchLink fieldCode="AR" term="%22Milutinović%2C+Veljko%22">Milutinović, Veljko</searchLink><br /><searchLink fieldCode="AR" term="%22Furht%2C+Borko%22">Furht, Borko</searchLink>
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  Data: Journal of Big Data; 7/26/2025, Vol. 12 Issue 1, p1-31, 31p
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  Data: <searchLink fieldCode="DE" term="%22Data+flow+computing%22">Data flow computing</searchLink><br /><searchLink fieldCode="DE" term="%22High+performance+computing%22">High performance computing</searchLink><br /><searchLink fieldCode="DE" term="%22Big+data%22">Big data</searchLink><br /><searchLink fieldCode="DE" term="%22Parallel+processing%22">Parallel processing</searchLink><br /><searchLink fieldCode="DE" term="%22Instruction+set+architecture%22">Instruction set architecture</searchLink><br /><searchLink fieldCode="DE" term="%22Benchmark+problems+%28Computer+science%29%22">Benchmark problems (Computer science)</searchLink>
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  Data: Dataflow computing has proved to be more efficient for certain high-performance computing algorithms. The prerequisites are that there is enough parallel calculation to cover the overhead of executing instructions on the dataflow hardware until the first result is ready. This is often true with algorithms that work with big data and that can process multiple iterations independently, e.g., while simulating certain phenomena in many elementary volumes. However, dataflow hardware runs typically at an order of magnitude lower frequencies compared to the control-flow processor. From a programmer's point of view, programming dataflow architectures is considerably harder than programming control-flow architectures. As a result, it is not always obvious whether programming dataflow architectures for certain algorithms is worth the effort needed. Therefore, there is a need for a programmer to be able to predict the outcome of programming for dataflow architectures in terms of accelerating program execution and power savings. This article presents a newly developed tool that a programmer can use for profiling control-flow algorithms and estimating the acceleration possibilities using the dataflow hardware. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of Journal of Big Data is the property of Springer Nature and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Text: English
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              M: 07
              Text: 7/26/2025
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