Academic Journal
An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA.
| Τίτλος: | An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA. |
|---|---|
| Συγγραφείς: | Yin, Xiaodi, Wu, Zhipeng, Li, Dejian, Shen, Chongfei, Liu, Yu |
| Πηγή: | IEEE Embedded Systems Letters; Jun2024, Vol. 16 Issue 2, p158-161, 4p |
| Περίληψη: | Field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As most CNN accelerators focus on dense neural networks, to solve the problem of difficult hardware deployment due to irregular networks, we propose a method for sparse neural networks in our work. The storage and coding format of sparse data obtained by the block pruning method is designed to make it friendly to implement on FPGA. Besides, we also propose an efficient and simple data flow by the planarization of the whole convolution calculation process. The experimental result demonstrates that our implementation can achieve clock frequency of 190 MHz, power consumption of 13.32 W and inferencing speed of 16.37 ms. Compared with some typical Mobilenet implementation schemes, our method has been proven to achieve a better balance between frequency, accuracy, power consumption, and speed. [ABSTRACT FROM AUTHOR] |
| Copyright of IEEE Embedded Systems Letters is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.) | |
| Βάση Δεδομένων: | Complementary Index |
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| Items | – Name: Title Label: Title Group: Ti Data: An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA. – Name: Author Label: Authors Group: Au Data: <searchLink fieldCode="AR" term="%22Yin%2C+Xiaodi%22">Yin, Xiaodi</searchLink><br /><searchLink fieldCode="AR" term="%22Wu%2C+Zhipeng%22">Wu, Zhipeng</searchLink><br /><searchLink fieldCode="AR" term="%22Li%2C+Dejian%22">Li, Dejian</searchLink><br /><searchLink fieldCode="AR" term="%22Shen%2C+Chongfei%22">Shen, Chongfei</searchLink><br /><searchLink fieldCode="AR" term="%22Liu%2C+Yu%22">Liu, Yu</searchLink> – Name: TitleSource Label: Source Group: Src Data: IEEE Embedded Systems Letters; Jun2024, Vol. 16 Issue 2, p158-161, 4p – Name: Abstract Label: Abstract Group: Ab Data: Field-programmable gate array (FPGA) has become an excellent hardware accelerator solution for convolutional neural networks (CNNs). Meanwhile, optimizing methods, such as model compression, have been proposed. As most CNN accelerators focus on dense neural networks, to solve the problem of difficult hardware deployment due to irregular networks, we propose a method for sparse neural networks in our work. The storage and coding format of sparse data obtained by the block pruning method is designed to make it friendly to implement on FPGA. Besides, we also propose an efficient and simple data flow by the planarization of the whole convolution calculation process. The experimental result demonstrates that our implementation can achieve clock frequency of 190 MHz, power consumption of 13.32 W and inferencing speed of 16.37 ms. Compared with some typical Mobilenet implementation schemes, our method has been proven to achieve a better balance between frequency, accuracy, power consumption, and speed. [ABSTRACT FROM AUTHOR] – Name: Abstract Label: Group: Ab Data: <i>Copyright of IEEE Embedded Systems Letters is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.) |
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| RecordInfo | BibRecord: BibEntity: Identifiers: – Type: doi Value: 10.1109/LES.2023.3296507 Languages: – Code: eng Text: English PhysicalDescription: Pagination: PageCount: 4 StartPage: 158 Titles: – TitleFull: An Efficient Hardware Accelerator for Block Sparse Convolutional Neural Networks on FPGA. Type: main BibRelationships: HasContributorRelationships: – PersonEntity: Name: NameFull: Yin, Xiaodi – PersonEntity: Name: NameFull: Wu, Zhipeng – PersonEntity: Name: NameFull: Li, Dejian – PersonEntity: Name: NameFull: Shen, Chongfei – PersonEntity: Name: NameFull: Liu, Yu IsPartOfRelationships: – BibEntity: Dates: – D: 01 M: 06 Text: Jun2024 Type: published Y: 2024 Identifiers: – Type: issn-print Value: 19430663 Numbering: – Type: volume Value: 16 – Type: issue Value: 2 Titles: – TitleFull: IEEE Embedded Systems Letters Type: main |
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