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LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.

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Τίτλος: LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
Συγγραφείς: TAMON SADASUE, TSUYOSHI ISSHIKI
Πηγή: IPSJ Transactions on System LSI Design Methodology; Feb2023, Vol. 16 Issue 1, p12-26, 15p
Θεματικοί όροι: Computer hardware description languages, Digital electronics, High level synthesis (Electronic design), Hardware design & construction, Systems design, Compilers (Computer programs)
Περίληψη: As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs. [ABSTRACT FROM AUTHOR]
Copyright of IPSJ Transactions on System LSI Design Methodology is the property of Information Processing Society of Japan and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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An: 175419361
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PubTypeId: academicJournal
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IllustrationInfo
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  Data: LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
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  Data: <searchLink fieldCode="AR" term="%22TAMON+SADASUE%22">TAMON SADASUE</searchLink><br /><searchLink fieldCode="AR" term="%22TSUYOSHI+ISSHIKI%22">TSUYOSHI ISSHIKI</searchLink>
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  Data: IPSJ Transactions on System LSI Design Methodology; Feb2023, Vol. 16 Issue 1, p12-26, 15p
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  Data: <searchLink fieldCode="DE" term="%22Computer+hardware+description+languages%22">Computer hardware description languages</searchLink><br /><searchLink fieldCode="DE" term="%22Digital+electronics%22">Digital electronics</searchLink><br /><searchLink fieldCode="DE" term="%22High+level+synthesis+%28Electronic+design%29%22">High level synthesis (Electronic design)</searchLink><br /><searchLink fieldCode="DE" term="%22Hardware+design+%26+construction%22">Hardware design & construction</searchLink><br /><searchLink fieldCode="DE" term="%22Systems+design%22">Systems design</searchLink><br /><searchLink fieldCode="DE" term="%22Compilers+%28Computer+programs%29%22">Compilers (Computer programs)</searchLink>
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  Label: Abstract
  Group: Ab
  Data: As the scale of digital circuit design increases, design and verification using conventional hardware description languages (HDLs), such as verilog-HDL and VHDL, limit efficiency. Consequently, high level synthesis (HLS), as well as domain specific languages (DSLs), which alternates conventional HDLs, are beginning to garner attention. We proposed a design framework that uses the C language as a register transfer level descriptive language. In this study, we introduced a LLVM compiler infrastructure to extend our previous work, support the C/C++ standard as the input code, and aggressively optimize the circuit design. In addition to supporting a single module generation, we extended our framework to support the hierarchical module description for efficient system design. We demonstrated the conversion of the input of C/C++ code into the verilog code, optimize its logic, and construct pipelined logic to achieve the original behavior in multiple clock cycles. Our framework offers a significantly efficient system-level hardware design and a powerful debugging environment with software development platforms and tool-sets. The generated hardware logic performs as well as or better than hand-written logic using conventional HDLs. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of IPSJ Transactions on System LSI Design Methodology is the property of Information Processing Society of Japan and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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RecordInfo BibRecord:
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        Value: 10.2197/ipsjtsldm.16.12
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      – Code: eng
        Text: English
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      Pagination:
        PageCount: 15
        StartPage: 12
    Subjects:
      – SubjectFull: Computer hardware description languages
        Type: general
      – SubjectFull: Digital electronics
        Type: general
      – SubjectFull: High level synthesis (Electronic design)
        Type: general
      – SubjectFull: Hardware design & construction
        Type: general
      – SubjectFull: Systems design
        Type: general
      – SubjectFull: Compilers (Computer programs)
        Type: general
    Titles:
      – TitleFull: LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure.
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            NameFull: TAMON SADASUE
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            NameFull: TSUYOSHI ISSHIKI
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            – D: 01
              M: 02
              Text: Feb2023
              Type: published
              Y: 2023
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            – TitleFull: IPSJ Transactions on System LSI Design Methodology
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