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Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.

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Τίτλος: Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.
Συγγραφείς: Javaheri, Fatemeh Negin, Morin-Allory, Katell, Borrione, Dominique
Πηγή: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; May2017, Vol. 36 Issue 5, p869-882, 14p
Θεματικοί όροι: Electric circuits, Debugging, Programming languages, Temporal integration, Engineering systems -- Computer simulation, Mathematical models
Περίληψη: We revisit the specification of control circuits and protocols written as regular expressions, and propose a synthesizable subset of the sequences that can be written in the property specification language and system Verilog assertions standards. We give a formal semantics of the sequence operators that can directly be interpreted in terms of circuits, and provide a modular method to achieve the automatic generation of compliant hardware from specifications written as temporal sequences. The method also generates assertions to check the completeness and consistency of the specifications. Results obtained on classical benchmarks show the efficiency of our technique. Finally, we discuss the applications of our prototype tool in an assertion-based verification flow. [ABSTRACT FROM AUTHOR]
Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)
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  Data: Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.
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  Data: <searchLink fieldCode="AR" term="%22Javaheri%2C+Fatemeh+Negin%22">Javaheri, Fatemeh Negin</searchLink><br /><searchLink fieldCode="AR" term="%22Morin-Allory%2C+Katell%22">Morin-Allory, Katell</searchLink><br /><searchLink fieldCode="AR" term="%22Borrione%2C+Dominique%22">Borrione, Dominique</searchLink>
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  Data: IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems; May2017, Vol. 36 Issue 5, p869-882, 14p
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  Data: <searchLink fieldCode="DE" term="%22Electric+circuits%22">Electric circuits</searchLink><br /><searchLink fieldCode="DE" term="%22Debugging%22">Debugging</searchLink><br /><searchLink fieldCode="DE" term="%22Programming+languages%22">Programming languages</searchLink><br /><searchLink fieldCode="DE" term="%22Temporal+integration%22">Temporal integration</searchLink><br /><searchLink fieldCode="DE" term="%22Engineering+systems+--+Computer+simulation%22">Engineering systems -- Computer simulation</searchLink><br /><searchLink fieldCode="DE" term="%22Mathematical+models%22">Mathematical models</searchLink>
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  Data: We revisit the specification of control circuits and protocols written as regular expressions, and propose a synthesizable subset of the sequences that can be written in the property specification language and system Verilog assertions standards. We give a formal semantics of the sequence operators that can directly be interpreted in terms of circuits, and provide a modular method to achieve the automatic generation of compliant hardware from specifications written as temporal sequences. The method also generates assertions to check the completeness and consistency of the specifications. Results obtained on classical benchmarks show the efficiency of our technique. Finally, we discuss the applications of our prototype tool in an assertion-based verification flow. [ABSTRACT FROM AUTHOR]
– Name: Abstract
  Label:
  Group: Ab
  Data: <i>Copyright of IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems is the property of IEEE and its content may not be copied or emailed to multiple sites without the copyright holder's express written permission. Additionally, content may not be used with any artificial intelligence tools or machine learning technologies. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract.</i> (Copyright applies to all Abstracts.)
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        Value: 10.1109/TCAD.2016.2600241
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      – SubjectFull: Debugging
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      – SubjectFull: Programming languages
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      – SubjectFull: Temporal integration
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      – SubjectFull: Engineering systems -- Computer simulation
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      – SubjectFull: Mathematical models
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      – TitleFull: Synthesis of Regular Expressions Revisited: From PSL SEREs to Hardware.
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              Text: May2017
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