Conference
A scheme for approximating decoder reduction in booth multipliers.
| Τίτλος: | A scheme for approximating decoder reduction in booth multipliers. |
|---|---|
| Συγγραφείς: | Goud, E. Naresh1 (AUTHOR) ediganareshgoud406@gmail.com, Mahesh, G.1 (AUTHOR) mahi23671@gmail.com, Parthasaradhi, C.1 (AUTHOR) parthups09@gmail.com, Kishore, T.1 (AUTHOR) talarikishore.718@gmail.com |
| Πηγή: | AIP Conference Proceedings. 2026, Vol. 3418 Issue 1, p1-9. 9p. |
| Θεματικοί όροι: | *Decoding algorithms, *Approximation theory, *Computer performance, *Mathematical optimization |
| Περίληψη: | This project presents a high-performance 32:8 decoder reduced approximation scheme for Booth multipliers that aims to optimize the multiplication of large binary numbers. The main goal is to approximate the process equations and minimize the component parts, thereby reducing computational complexity, area, and power consumption. Using the reduced decoder scheme, the designer produces an 8-bit output from two 32-bit inputs, while also reducing the Normalized Mean Error Deviation (NMED), thus minimizing the introduced error. The design also integrates high-speed adders optimized to reduce delays during the addition operation, significantly improving the overall efficiency of the Booth multiplier. The performance evaluation of a design covers various key metrics such as area, speed, power, delay, and throughput. Using efficient and predictable methods can reduce power consumption and increase speed while reducing overall hardware area. Additionally, the implementation is evaluated using lookup tables (LUTs), transfer level registers (RTL) diagrams, and display connections to ensure that the design is designed for real-world hardware usage. Compared to the traditional Booth multiplier, the scheme provides significant improvements in performance and hardware efficiency. [ABSTRACT FROM AUTHOR] |
| Βάση Δεδομένων: | Academic Search Index |
καταχωρήστε σχόλιο πρώτοι!