Design and Implementation of a Small-Scale Batch Mixing System using RISC-V Architecture

Συγγραφείς: Mukherjee, Angira, Kar, Debjit, Padhan, Pragyan Parimita, Kumar, Vineet, Lata, Nutan, Pranav, Prashant, Smita, Apurva, Anjum, Nikhat, Kumar, Priyanshu, Sengupta, Aditya Sankar, Kumari, Pooja, Nath, Vijay

Πηγή: 2025 13th International Conference on Intelligent Systems and Embedded Design (ISED) Intelligent Systems and Embedded Design (ISED), 2025 13th International Conference on. :253-258 Dec, 2025

Relation: 2025 13th International Conference on Intelligent Systems and Embedded Design (ISED)

Advancing the RISC-V Performance Simulation Ecosystem with Data Prefetching

Συγγραφείς: Crespo, Luís^Aff11, Neves, Nuno^Aff11, Tomas, Pedro^Aff11, Roma, Nuno^Aff11

Συνεισφορές: Goos, Gerhard, Founding Editor^Aff1, Hartmanis, Juris, Founding Editor^Aff2, Bertino, Elisa, Editorial Board Member^Aff3, Gao, Wen, Editorial Board Member^Aff4, Steffen, Bernhard, Editorial Board Member^Aff5, Yung, Moti, Editorial Board Member^Aff6, Neuwirth, Sarah, editor^Aff7, Paul, Arnab Kumar, editor^Aff8, Weinzierl, Tobias, editor^Aff9, Carson, Erin Claire, editor^Aff10

Πηγή: High Performance Computing : ISC High Performance 2025 International Workshops, Hamburg, Germany, June 10–13, 2025, Revised Selected Papers. 16091:548-561

SpecCheck: A Tool for Systematic Identification of Vulnerable Transient Execution in gem5

Συγγραφείς: McKevitt, Zack, Trivedi, Ashutosh, Lehman, Tamara Silbergleit

Πηγή: Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques. :265-278

Διαθεσιμότητα: http://dl.acm.org/doi/10.1109/PACT58117.2023.00030

Metamorphic Edge Processor Simulation Framework Using Flexible Runtime Partial Replacement of Software-Embedded Verilog RTL Models

Συγγραφείς: Kwon, Jisu, Oh, Sejong, Park, Daejin

Πηγή: 2021 IEEE International Symposium on Circuits and Systems (ISCAS). :1-5 May, 2021

Relation: 2021 IEEE International Symposium on Circuits and Systems (ISCAS)

CodeAPeel: An Integrated and Layered Learning Technology For Computer Architecture Courses

Συγγραφείς: Oruç, Ahmet Yavuz, Author, Atmaca, Abdullah, Author, Sengun, Yusuf Nevzat, Author, Yenimol, Ali Semi, Author

Συνεισφορές: Oruç, Ahmet Yavuz, Author, Atmaca, Abdullah, Author, Sengun, Yusuf Nevzat, Author, Yenimol, Ali Semi, Author

Πηγή: Computing Research Repository (CoRR). abs/2104.09502

Θεματικοί όροι: Assembly-language, computer architecture, frame buffer, graphics, learning technology, processor simulation, SISD processor, SIMD processor, screen programming, vector processing.

Περιγραφή αρχείου: print

Σύνδεσμος πρόσβασης: https://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-544383
https://doi.org/10.48550/arXiv.2104.09502

iQ: An Efficient and Flexible Queue-Based Simulation Framework

Συγγραφείς: Roca, Damian, Nemirovsky, Daniel, Casas, Marc, Moreto, Miquel, Valero, Mateo, Nemirovsky, Mario

Πηγή: 2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS) MASCOTS Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), 2017 IEEE 25th International Symposium on. :143-149 Sep, 2017

Relation: 2017 IEEE 25th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS)

Simulating a pipelined RISC processor

Συγγραφείς: Pandey, Amit

Πηγή: 2016 International Conference on Inventive Computation Technologies (ICICT) Inventive Computation Technologies (ICICT), International Conference on. 2:1-6 Aug, 2016

Relation: 2016 International Conference on Inventive Computation Technologies (ICICT)

A performance-conserving approach for reducing peak power consumption in server systems

Συγγραφείς: Felter, Wes, Rajamani, Karthick, Keller, Tom, Rusu, Cosmin

Πηγή: Proceedings of the 19th annual international conference on Supercomputing. :293-302

Διαθεσιμότητα: http://dl.acm.org/doi/10.1145/1088149.1088188

Hybrid Simulation for Energy Estimation of Embedded Software

Συγγραφείς: Muttreja, A., Raghunathan, A., Ravi, S., Jha, N. K.

Πηγή: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 26(10):1843-1854 Oct, 2007

Automated Energy/Performance Macromodeling of Embedded Software

Συγγραφείς: Muttreja, A., Raghunathan, A., Ravi, S., Jha, N. K.

Πηγή: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 26(3):542-552 Mar, 2007

PROJECT GRAMS: A graphical reconfigurable architecture MIPS simulator

Συγγραφείς: Bautista, Patrick Ian, Cruz, Arnold, Rio, Amor Corazon, Reyes, Joy Alinda

Πηγή: TENCON 2008 - 2008 IEEE Region 10 Conference. :1-5 Nov, 2008

Relation: TENCON 2008 - 2008 IEEE Region 10 Conference (TENCON)

A component-based visual simulator for MIPS32 processors

Συγγραφείς: Sarjoughian, Hessam, Chen, Yu, Burger, Kevin

Πηγή: 2008 38th Annual Frontiers in Education Conference Frontiers in Education Conference, 2008. FIE 2008. 38th Annual. :F3B-9-F3B-14 Oct, 2008

Relation: 2008 IEEE Frontiers in Education Conference (FIE)

Facile : a language and compiler for high-performance processor simulators

Συγγραφείς: Schnarr, Eric C., Hill, Mark D., Larus, James R.

Πηγή: ACM SIGPLAN Notices. 36(5):321-331

Διαθεσιμότητα: http://dl.acm.org/doi/10.1145/381694.378864

Fast out-of-order processor simulation using memoization

Συγγραφείς: Schnarr, Eric, Larus, James R.

Πηγή: ACM SIGOPS Operating Systems Review. 32(5):283-294

Διαθεσιμότητα: http://dl.acm.org/doi/10.1145/384265.291063

Efficient in-system RTL verification and debugging using FPGAs (abstract only)

Συγγραφείς: Saha, Proshanta, Haymes, Chuck, Bellofatto, Ralph, Brezzo, Bernard, Kapur, Mohit, Asaad, Sameh

Πηγή: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays. :269-269

Διαθεσιμότητα: http://dl.acm.org/doi/10.1145/2145694.2145753

McPAT-PVT: Delay and Power Modeling Framework for FinFET Processor Architectures Under PVT Variations

Συγγραφείς: Tang, A., Yang, Y., Lee, C., Jha, N.K.

Πηγή: IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE Trans. VLSI Syst. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. 23(9):1616-1627 Sep, 2015

DSP processor/compiler co-design : a quantitative approach

Συγγραφείς: Zivojnovic, V., Pees, S., Schlager, C., Willems, M., Schoenen, R., Meyr, H.

Πηγή: Proceedings of the 9th international symposium on System synthesis. :108

Διαθεσιμότητα: http://dl.acm.org/doi/10.5555/524431.857914

Bringing real processors to labs

Συγγραφείς: Crispín Gómez Requena, María Engracia Gómez, Julio Sahuquillo

Συνεισφορές: Departamento de Informática de Sistemas y Computadores, Escuela Técnica Superior de Ingeniería Informática, Grupo de Arquitecturas Paralelas, Ministerio de Economía y Competitividad, Repositorio Institucional de la Universitat Politècnica de València Riunet

Πηγή: RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
instname
Universitat Politècnica de València (UPV)

Θεματικοί όροι: ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES, Multicore processors, 05 social sciences, 0202 electrical engineering, electronic engineering, information engineering, Computer architecture, 02 engineering and technology, Lab sessions, Processor simulation, 0503 education, 3. Good health

Περιγραφή αρχείου: application/pdf

Σύνδεσμος πρόσβασης: https://riunet.upv.es/bitstream/10251/75304/3/paper-reviewed.pdf
https://riunet.upv.es/handle/10251/75304

Modelado de una arquitectura de monitorización de prestaciones para el simulador gem5 ; Modeling a Performance Monitoring Architecture for the gem5 Simulator ; Modelatge d'una arquitectura de monitorització de prestacions per al simulador gem5

Συγγραφείς: Pecino-Fernández, Manuel Antonio

Συνεισφορές: Petit Martí, Salvador Vicente, Sahuquillo Borrás, Julio, Departamento de Informática de Sistemas y Computadores, Escuela Técnica Superior de Ingeniería Informática, Grupo de Arquitecturas Paralelas

Θεματικοί όροι: Monitorización y evaluación de prestaciones, Gem5, Microarquitectura, Análisis Top-Down, Simulación de Procesador, PMU, Performance monitoring and evaluation, Microarchitecture, Top-Down Analysis, Processor Simulation, ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES, Grado en Ingeniería Informática-Grau en Enginyeria Informàtica

Περιγραφή αρχείου: application/pdf

Relation: https://riunet.upv.es/handle/10251/207283

Διαθεσιμότητα: https://riunet.upv.es/handle/10251/207283

Modelado de una arquitectura de monitorización de prestaciones para el simulador gem5

Συγγραφείς: Pecino-Fernández, Manuel Antonio

Συνεισφορές: Petit Martí, Salvador Vicente, Sahuquillo Borrás, Julio, Departamento de Informática de Sistemas y Computadores, Escuela Técnica Superior de Ingeniería Informática, Grupo de Arquitecturas Paralelas, Repositorio Institucional de la Universitat Politècnica de València Riunet

Πηγή: RiuNet. Repositorio Institucional de la Universitat Politécnica de Valéncia
Universitat Politècnica de València (UPV)

Θεματικοί όροι: ARQUITECTURA Y TECNOLOGIA DE COMPUTADORES, Monitorización y evaluación de prestaciones, Simulación de Procesador, Grado en Ingeniería Informática-Grau en Enginyeria Informàtica, Top-Down Analysis, Microarquitectura, Processor Simulation, PMU, Microarchitecture, Gem5, Análisis Top-Down, Performance monitoring and evaluation

Περιγραφή αρχείου: application/pdf

Σύνδεσμος πρόσβασης: https://riunet.upv.es/handle/10251/207283