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1Academic Journal
Source: The Herald of the Siberian State University of Telecommunications and Information Science; Том 19, № 1 (2025); 65-79 ; Вестник СибГУТИ; Том 19, № 1 (2025); 65-79 ; 1998-6920 ; 10.55648/1998-6920-2025-19-1
Subject Terms: улучшение качества, algorithm hardware implementation, Verilog, visibility, contrast, linear contrast enhancement, fog, mist, FPGA, quality improvement, аппаратная реализация алгоритмов, видимость, контраст, линейное контрастирование, туман, дымка, ПЛИС
File Description: application/pdf
Relation: https://vestnik.sibsutis.ru/jour/article/view/803/786; https://vestnik.sibsutis.ru/jour/article/downloadSuppFile/803/20; https://vestnik.sibsutis.ru/jour/article/downloadSuppFile/803/21; Михайлюк Ю. П., Начаров Д. В. Метод улучшения различимости объектов на цифровых изображениях, полученных в условиях недостаточной видимости // Журнал радиоэлектроники [электронный журнал]. 2015. No6.; He K., Sun J., Tang X. Single Image Haze Removal Using Dark Channel Prior // Proc. of the 2009 IEEE Conference on Computer Vision and Pattern Recognition, 2009. P. 1956–1963.; Tarel J. -P., Hautiere N., Caraffa L., Cord A., Halmaoui H., Gruyer D. Vision Enhancement in Homogeneous and Heterogeneous Fog // IEEE Intelligent Transportation Systems Magazine. 2012. V. 4, Is. 2, P. 6–20.; Duminil A., Tarel J. -P., Brémond R. Single Image Atmospheric Veil Removal Using New Priors // Proc. of the 2021 IEEE International Conference on Image Processing (ICIP). 2021. P. 1719–1723.; Zhang J., Li F., Kang M., Luo X., Zhao J., Xiao Ch., Du H., Wang H. A Method of Image Dehazing Based on Atmospheric Veil Prediction by ResNet // Proc. of the 2nd Workshop on User-centric Narrative Summarization of Long Videos. 2023. P. 17–24.; Varalakshmi J., Jose D., Kumar P. N. FPGA Implementation of Haze Removal Technique Based on Dark Channel Prior // Computational Vision and Bio-Inspired Computing (ICCVBIC 2021), 2021. P. 624–630.; Cyclone V Device Overview : technical description [Электронный ресурс]. URL: https://www.altera.com/en_US/pdfs/literature/hb/cyclone-v/cv_51001.pdf (дата обращения: 20.04.2023).; ADV7123 technical description [Электронный ресурс]. URL: http://www.analog.com/media/en/technical-documentation/data-sheets/ADV7123.pdf (дата обращения: 20.04.2023).; Altera Phase-Locked Loop IP Core User Guide : technical description [Электронный ресурс] URL:https://www.altera.com/en_US/pdfs/literature/ug/altera_pll.pdf (дата обращения: 20.04.2023); Kumar A. K., Jeevaratnam N., Patnaik S. On-Chip Memory for Image Processing Applications Based on FPGA // Proc. of the International conference on Signal Processing, Communication, Power and Embedded System, 2016. P.1598–1602.; Licciardo G. D., Cappetta C., Di Benedetto L. FPGA Optimization of Convolution-based 2D Filtering Processor for Image Processing // Proc. of the 8th Computer Science and Electronic Engineering Conference, 2016. P.180–185; https://vestnik.sibsutis.ru/jour/article/view/803
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2Academic Journal
Authors: Yahi, Amira, Toumi, Salah, Bourennane, El-Bay, Messaoudi, Kamel
Contributors: Bourennane, El-Bay
Source: Evolving Systems. 7:233-241
Subject Terms: Video compression H.264/AVC Full search block matching algorithm Hardware implementation Parallel processors, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, [SPI.TRON] Engineering Sciences [physics]/Electronics, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems
Linked Full TextAccess URL: https://link.springer.com/article/10.1007/s12530-015-9140-6/fulltext.html
https://dblp.uni-trier.de/db/journals/evs/evs7.html#YahiTBM16
https://hal.archives-ouvertes.fr/hal-01279862v1
https://link.springer.com/article/10.1007/s12530-015-9140-6
https://hal.inria.fr/hal-01279862v1