Real-Time Systems Development with RTEMS and Multicore Processors

Authors: Bloom, Gedare, Sherrill, Joel, Hu, Tingting, Bertolotti, Ivan Cibrario

Subject Terms: Interrupt Handler, Internet-of-things, Mutual Exclusion Semaphore, Real-time executive for multiprocessor systems, Priority Ceiling Protocol, Cyber-physical systems, High Priority Task, Real-time operating system, Priority Inheritance Protocol, Execution Time, Scheduling Algorithms, Critical Region, Worst Case Execution Time, Task Control Block, Worst Case Response Time, Interrupt Request, Cache Line, Rate Monotonic, Context Switch, Protocol Stack, Low Priority Task, Struct Timeval, Embedded Systems, Write Operation, Computer architecture and logic design, Supercomputers, Electronics engineering, Energy, power generation, distribution and storage

File Description: application/pdf

Relation: Embedded Systems

Access URL: https://library.oapen.org/handle/20.500.12657/101536

On the Design and Implementation of Real-Time Resource Access Protocols

Authors: dos Santos, Lucas Matheus, Gracioli, Giovani, Kloda, Tomasz, Caccamo, Marco

Source: 2020 X Brazilian Symposium on Computing Systems Engineering (SBESC) Computing Systems Engineering (SBESC), 2020 X Brazilian Symposium on. :1-8 Nov, 2020

Relation: 2020 X Brazilian Symposium on Computing Systems Engineering (SBESC)

Precise Worst-Case Blocking Time of Tasks Under Priority Inheritance Protocol

Authors: Faldella, E., Loreti, D.

Source: IEEE Transactions on Computers IEEE Trans. Comput. Computers, IEEE Transactions on. 70(11):1901-1913 Nov, 2021

FT-PIP: Flush Task Incorporated Priority-Inheritance Protocol to Reduce Information Leakage on Multiprocessor Real-Time Systems

Authors: Baek, H., Lee, J.

Source: IEEE Access Access, IEEE. 9:81882-81894 2021

Supporting single and multi-core resource access protocols on object-oriented RTOSes

Authors: Lucas Matheus dos Santos, Giovani Gracioli, Tomasz Kloda, Marco Caccamo

Contributors: Kloda, Tomasz, Federal University of Santa Caterina, Florianopolis, Brazil, Institut National des Sciences Appliquées (INSA), Équipe Verification de Systèmes Temporisés Critiques (LAAS-VERTICS), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Technische Universität Munchen - Technical University Munich - Université Technique de Munich (TUM)

Source: Design Automation for Embedded Systems. 27:31-50

Subject Terms: Economics, 0102 computer and information sciences, 02 engineering and technology, Multiprocessor Scheduling, 01 natural sciences, Priority ceiling protocol, Priority inheritance protocol, Resource Allocation, Multicore Architectures, Parallel Computing and Performance Optimization, RTOS, 0202 electrical engineering, electronic engineering, information engineering, Real-time operating systems, Embedded system, Real-time systems, Real-time operating system, Performance Optimization, Real-Time Scheduling in Embedded Systems, Reconfigurable Computing Systems and Design Methods, Computer science, Distributed computing, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Resource access protocols, Overhead (engineering), Operating system, Operations management, Hardware and Architecture, Computer Science, Physical Sciences, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, MrsP, Scheduling (production processes), Stack resource policy

File Description: application/pdf

A predictable interrupt management policy for real-time operating systems

Authors: Amiri, J.E., Kargahi, M.

Source: 2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST) Real-Time and Embedded Systems and Technologies (RTEST), 2015 CSI Symposium on. :1-8 Oct, 2015

Relation: 2015 CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST)

Research on Subsystem Hybrid Scheduling and Priority Inversion Based uCOS-II

Authors: Wang, X., Liu, T.

Source: 2012 Fifth International Conference on Intelligent Networks and Intelligent Systems Intelligent Networks and Intelligent Systems (ICINIS), 2012 Fifth International Conference on. :117-121 Nov, 2012

Relation: 2012 5th International Conference on Intelligent Networks and Intelligent Systems (ICINIS)

Real-Time Systems Development with RTEMS and Multicore Processors

Authors: Bloom, Gedare, Sherrill, Joel, Hu, Tingting, Bertolotti, Ivan Cibrario

Subject Terms: Interrupt Handler, Internet-of-things, Mutual Exclusion Semaphore, Real-time executive for multiprocessor systems, Priority Ceiling Protocol, Cyber-physical systems, High Priority Task, Real-time operating system, Priority Inheritance Protocol, Execution Time, Scheduling Algorithms, Critical Region, Worst Case Execution Time, Task Control Block, Worst Case Response Time, Interrupt Request, Cache Line, Rate Monotonic, Context Switch, Protocol Stack, Low Priority Task, Struct Timeval, Embedded Systems, Write Operation, Computer architecture and logic design, Supercomputers, Electronics engineering, Energy, power generation, distribution and storage

File Description: image/jpeg

Relation: Embedded Systems

Access URL: https://directory.doabooks.org/handle/20.500.12854/148278
https://library.oapen.org/handle/20.500.12657/95789
https://library.oapen.org/bitstream/20.500.12657/95789/1/9781351255783.pdf

Real-Time Systems Development with RTEMS and Multicore Processors

Authors: Bloom, Gedare, Sherrill, Joel, Hu, Tingting, Bertolotti, Ivan Cibrario

Subject Terms: Interrupt Handler, Internet-of-things, Mutual Exclusion Semaphore, Real-time executive for multiprocessor systems, Priority Ceiling Protocol, Cyber-physical systems, High Priority Task, Real-time operating system, Priority Inheritance Protocol, Execution Time, Scheduling Algorithms, Critical Region, Worst Case Execution Time, Task Control Block, Worst Case Response Time, Interrupt Request, Cache Line, Rate Monotonic, Context Switch, Protocol Stack, Low Priority Task, Struct Timeval, Embedded Systems, Write Operation, Computer architecture and logic design, Supercomputers, Electronics engineering, Energy, power generation, distribution and storage

File Description: image/jpeg

Relation: Embedded Systems

Access URL: https://directory.doabooks.org/handle/20.500.12854/159291
https://library.oapen.org/handle/20.500.12657/101536
https://library.oapen.org/bitstream/20.500.12657/101536/1/9781351255783.pdf

A Dynamic Scheduling Model for Real-Time Tasks in Reliable System

Authors: Jie, Zhang, Fumin, Yang, Gang, Tu

Source: 2009 International Conference on Networks Security, Wireless Communications and Trusted Computing Networks Security, Wireless Communications and Trusted Computing, 2009. NSWCTC '09. International Conference on. 2:185-188 Apr, 2009

Relation: 2009 International Conference on Networks Security, Wireless Communications and Trusted Computing (NSWCTC)

Real-Time Systems Development with RTEMS and Multicore Processors

Authors: Gedare Bloom, Joel Sherrill, Tingting Hu, Ivan Cibrario Bertolotti

Source: Boca Raton, Florida: CRC press, Taylor and Francis Group, 2020
info:cnr-pdr/source/autori:Gedare Bloom; Joel Sherrill; Tingting Hu; Ivan Cibrario Bertolotti/titolo:Real-Time Systems Development with RTEMS and Multicore Processors/editore: /anno:2020

Subject Terms: Struct Timeval, Embedded systems, Real-time executive for multiprocessor systems, Write Operation, thema EDItEUR::U Computing and Information Technology::UK Computer hardware::UKC Supercomputers, Priority Ceiling Protocol, Mutual Exclusion Semaphore, High Priority Task, Real-time operating systems, Real-time operating system, Critical Region, Protocol Stack, thema EDItEUR::U Computing and Information Technology::UY Computer science::UYF Computer architecture and logic design, thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TH Energy technology and engineering::THY Energy, power generation, distribution and storage, Cache Line, Interrupt Handler, Cyber-physical systems, thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering, Task Control Block, Interrupt Request, Priority Inheritance Protocol, Context Switch, Worst Case Response Time, Execution Time, Embedded software development, Worst Case Execution Time, Scheduling Algorithms, Rate Monotonic, Embedded Systems, Internet-of-things, Low Priority Task

File Description: image/jpeg; application/pdf

Access URL: https://directory.doabooks.org/handle/20.500.12854/148278
https://library.oapen.org/bitstream/20.500.12657/95789/1/9781351255783.pdf
https://library.oapen.org/handle/20.500.12657/95789
http://www.cnr.it/prodotto/i/441147
https://publications.cnr.it/doc/441147
https://www.routledge.com/Real-Time-Systems-Development-with-RTEMS-and-Multicore-Processors/Bloom-Sherrill-Hu-Bertolotti/p/book/9780815365976
https://library.oapen.org/handle/20.500.12657/101536
https://www.taylorfrancis.com/books/9781351255790

Priority Inheritance Protocol Proved Correct

Authors: Zhang, Xingyuan, Urban, Christian^{Aff2, cor2}, Wu, Chunhan

Source: Journal of Automated Reasoning. :1-23

Real-Time Systems Development with RTEMS and Multicore Processors ; 9781351255783.pdf

Authors: Bloom, Gedare, Sherrill, Joel, Hu, Tingting, Bertolotti, Ivan Cibrario

Subject Terms: Interrupt Handler, Internet-of-things, Mutual Exclusion Semaphore, Real-time executive for multiprocessor systems, Priority Ceiling Protocol, Cyber-physical systems, High Priority Task, Real-time operating system, Priority Inheritance Protocol, Execution Time, Scheduling Algorithms, Critical Region, Worst Case Execution Time, Task Control Block, Worst Case Response Time, Interrupt Request, Cache Line, Rate Monotonic, Context Switch, Protocol Stack, Low Priority Task, Struct Timeval, Embedded Systems, Write Operation

File Description: application/pdf

Relation: Embedded Systems; ONIX_20241209_9781351255783_11; https://www.taylorfrancis.com/books/9781351255790

Availability: https://library.oapen.org/handle/20.500.12657/95789
https://hdl.handle.net/20.500.12657/95789
https://www.taylorfrancis.com/books/9781351255790

Real-Time Systems Development with RTEMS and Multicore Processors

Authors: Bloom, Gedare, Sherrill, Joel, Hu, Tingting, Bertolotti, Ivan Cibrario

Subject Terms: Interrupt Handler, Internet-of-things, Mutual Exclusion Semaphore, Real-time executive for multiprocessor systems, Priority Ceiling Protocol, Cyber-physical systems, High Priority Task, Real-time operating system, Priority Inheritance Protocol, Execution Time, Scheduling Algorithms, Critical Region, Worst Case Execution Time, Task Control Block, Worst Case Response Time, Interrupt Request, Cache Line, Rate Monotonic, Context Switch, Protocol Stack, Low Priority Task, Struct Timeval, Embedded Systems, Write Operation, thema EDItEUR::U Computing and Information Technology::UY Computer science::UYF Computer architecture and logic design, thema EDItEUR::U Computing and Information Technology::UK Computer hardware::UKC Supercomputers, thema EDItEUR::T Technology, Engineering, Agriculture, Industrial processes::TJ Electronics and communications engineering::TJF Electronics engineering

File Description: image/jpeg

Relation: Embedded Systems; ONIX_20241209_9781351255783_11; https://library.oapen.org/handle/20.500.12657/95789; https://library.oapen.org/bitstream/20.500.12657/95789/1/9781351255783.pdf

Availability: https://library.oapen.org/handle/20.500.12657/95789
https://hdl.handle.net/20.500.12657/95789
https://directory.doabooks.org/handle/20.500.12854/148278
https://hdl.handle.net/20.500.12854/148278
https://library.oapen.org/bitstream/20.500.12657/95789/1/9781351255783.pdf

Priority Inheritance Protocol Proved Correct

Authors: Xingyuan Zhang, Christian Urban, Chunhan Wu

Contributors: Beringer, Lennart, Felty, Amy

Source: Lecture Notes in Computer Science ISBN: 9783642323461
Zhang, X, Urban, C & Wu, C 2020, ' Priority Inheritance Protocol Proved Correct ', JOURNAL OF AUTOMATED REASONING, vol. 64, no. 1, pp. 73-95 . https://doi.org/10.1007/s10817-019-09511-5

Subject Terms: Formal correctness proof, 0202 electrical engineering, electronic engineering, information engineering, 02 engineering and technology, Isabelle/HOL, Real-time systems, Priority Inheritance Protocol

File Description: application/pdf

Access URL: https://kclpure.kcl.ac.uk/portal/files/118825024/Priority_Inheritance_Protocol_Proved_ZHANG_Publishedonline12February2019_GOLD_VoR_CC_BY_.pdf
https://link.springer.com/content/pdf/10.1007/s10817-019-09511-5.pdf
https://link.springer.com/chapter/10.1007/978-3-642-32347-8_15
https://doi.org/10.1007/978-3-642-32347-8_15
https://kclpure.kcl.ac.uk/portal/en/publications/priority-inheritance-protocol-proved-correct(97daf087-4f9f-4689-90d0-8743ea85ff61).html
https://dblp.uni-trier.de/db/journals/jar/jar64.html#ZhangUW20
https://link.springer.com/article/10.1007/s10817-019-09511-5
https://core.ac.uk/display/29908156
https://rd.springer.com/chapter/10.1007/978-3-642-32347-8_15
https://paperity.org/p/185911641/priority-inheritance-protocol-proved-correct
https://kclpure.kcl.ac.uk/en/publications/97daf087-4f9f-4689-90d0-8743ea85ff61
https://kclpure.kcl.ac.uk/portal/en/publications/97daf087-4f9f-4689-90d0-8743ea85ff61

Dual ceiling protocol for real-time synchronization under preemption threshold scheduling

Authors: Saehwa Kim

Source: Journal of Computer and System Sciences. 76:741-750

Subject Terms: Computer Networks and Communications, Priority inversion problem, Applied Mathematics, Real-time scheduling, 02 engineering and technology, Real-time synchronization protocol, Priority ceiling protocol, Real-time object-oriented modeling, Priority inheritance protocol, Theoretical Computer Science, Schedulability analysis, Computational Theory and Mathematics, Preemption threshold scheduling, 0202 electrical engineering, electronic engineering, information engineering

Access URL: https://core.ac.uk/display/82321164
https://www.sciencedirect.com/science/article/pii/S0022000010000279
https://www.sciencedirect.com/science/article/abs/pii/S0022000010000279
https://dblp.uni-trier.de/db/journals/jcss/jcss76.html#Kim10

Capacidades de tiempo real del sistema operativo para IoT Zephyr

Authors: San Sebastián Sáiz, Adrián

Contributors: Pérez Tijero, Héctor, Aldea Rivas, Mario, Universidad de Cantabria

Source: UCrea Repositorio Abierto de la Universidad de Cantabria
instname

Subject Terms: POSIX, Desarrollo cruzado, Compilación cruzada, IoT, Test de rendimiento, Framework, Internet of Things, Zephyr, MaRTE OS, Benchmark, Internet de las cosas, Semáforo, Cross platform development, Universal Synchronous and Asynchronous serial Receiver and Transmitter, Mutex, Transmisor/Receptor universal síncrono/asíncrono en serie, RTOS, Interfaz del sistema operativo portable, Real-time operating system, Ordenador con conjunto de instrucciones reducido, Cross compiler, Herencia de prioridades, RISC, PIP, Portable Opeating System Interface, Priority Inheritance Protocol, Reduced Instruction Set Computer, USART, Sistema operativo de tiempo real

Access URL: https://hdl.handle.net/10902/30738

synchronizations shared resource access protocols

Authors: Midonnet, Serge, Fauberteau, Frédéric

Contributors: Ligm, Admin

Subject Terms: unbounded priority inversion, dead lock, chained blocking, blocking factor, priority ceiling protocol (PCP), multiprocessor systems, [INFO.INFO-DS] Computer Science [cs]/Data Structures and Algorithms [cs.DS], synchronization, stack resource policy (SRP) protocol, priority inheritance protocol (PIP), uniprocessor systems

Access URL: https://hal.archives-ouvertes.fr/hal-01087672

An Improved Priority Ceiling Protocol to Reduce Context Switches in Task Synchronization

Authors: Albert M. K. Cheng, Fan Jiang

Contributors: The Pennsylvania State University CiteSeerX Archives

Source: http://www.cs.uh.edu/docs/cosc/technical-reports/2005/05_23.pdf.

Subject Terms: concurrent programming, context-switching, task synchronization, Priority Inheritance Protocol, Priority Ceiling Protocol

File Description: application/pdf

Relation: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.211.1317

Availability: http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.211.1317
http://www.cs.uh.edu/docs/cosc/technical-reports/2005/05_23.pdf

A Process Algebraic Approach to the Schedulability Analysis of Real-Time Systems

Authors: Ben-Abdallah, Hanene, Choi, Jin-Young, Clarke, Duncan, Kim, Young Si, Lee, Insup, Xie, Hong-Liang

Source: Real-Time Systems: The International Journal of Time-Critical Computing Systems. November 1998 15(3):189-219