Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis

Authors: Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang

Source: Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays. :211-222

Subject Terms: Parallel computing, Cement, Computer hardware, Low-Power VLSI Circuit Design and Optimization, Reconfigurable Computing Systems and Design Methods, Computer science, Materials science, Field-programmable gate array, Systems engineering, 12. Responsible consumption, Engineering, Hardware and Architecture, Design cycle, Computer Science, Physical Sciences, Metallurgy, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, Computer architecture, Electrical and Electronic Engineering, Embedded system

ExDe: Design space exploration of scheduler architectures and mechanisms for serverless data-processing

Authors: Sacheendra Talluri, Nikolas Herbst, Cristina L. Abad, Tiziano De Matteis, Alexandru Iosup

Source: Future Generation Computer Systems. 153:84-96

Subject Terms: FOS: Computer and information sciences, Design, Computer Networks and Communications, Economics, Performance, Serverless, Workload, Cloud Computing and Big Data Technologies, 7. Clean energy, Distributed Grid Computing Systems, Architecture, Parallel Computing and Performance Optimization, Computer architecture, Embedded system, Design space exploration, Scheduler, Computer science, Distributed computing, Task Scheduling, Operating system, Operations management, Hardware and Architecture, Computer Science, Physical Sciences, Mechanism, Scheduling (production processes), Software, Information Systems

Access URL: https://research.vu.nl/en/publications/58b0ff29-2f35-4fe5-b0f0-1a759a596cc1
https://hdl.handle.net/1871.1/58b0ff29-2f35-4fe5-b0f0-1a759a596cc1
https://doi.org/10.1016/j.future.2023.11.013

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition

Authors: Liqiang Lu, Zizhang Luo, Size Zheng, Jieming Yin, Jason Cong, Yun Liang, Jianwei Yin

Source: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 43:1177-1190

Subject Terms: Parallel computing, Computer Networks and Communications, Latency (audio), 7. Clean energy, Multicore Architectures, 11. Sustainability, Parallel Computing and Performance Optimization, Computer architecture, Embedded system, Design space exploration, Computer network, Performance Optimization, 15. Life on land, Reconfigurable Computing Systems and Design Methods, Computer science, Interconnection, Distributed computing, Programming language, Overhead (engineering), Benchmarking, Networks on Chip in System-on-Chip Design, Hardware and Architecture, Computer Science, Physical Sciences, Reconfigurable Computing, Dataflow, Telecommunications, Dataflow Programming Languages

Investigating and Reducing the Architectural Impact of Transient Faults in Special Function Units for GPUs

Authors: Rodriguez Condia, Josie E., Guerrero-Balaguera, Juan-David, Patiño Núñez, Edwar J., Limas, Robert, Sonza Reorda, Matteo

Source: Journal of Electronic Testing. 40:215-228

Subject Terms: Parallel computing, Computational science, Fault Tolerance, Evolutionary biology, 02 engineering and technology, Computer science, 01 natural sciences, Programming language, Fault Tolerance in Electronic Systems, Engineering, Hardware and Architecture, Function (biology), Physical Sciences, Computer Science, 0103 physical sciences, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, 0202 electrical engineering, electronic engineering, information engineering, Graphics processing units (GPUs), Fault-tolerance, Reliability evaluation, Special function unit (SFU), T-Stream core, GPU Computing, Electrical and Electronic Engineering, Transient Faults, Very Large Scale Integration Testing, Biology, Transient (computer programming)

File Description: application/pdf

CTLA: Compressed Table Look up Algorithm for Open Flow Switch

Authors: Veeramani Sonai, Indira Bharathi, Muthaiah Uchimucthu, Sountharrajan S, Durga Prasad Bavirisetti

Source: IEEE Open Journal of the Computer Society, Vol 5, Pp 73-82 (2024)
IEEE Open Journal of the Computer Society (OJ-CS)

Subject Terms: Table (database), Computer Networks and Communications, Geometry, Information technology, 7. Clean energy, Distributed Grid Computing Systems, IP look-up, Parallel Computing and Performance Optimization, FOS: Mathematics, TCAM, Data mining, Performance Optimization, QA75.5-76.95, T58.5-58.64, Reconfigurable Computing Systems and Design Methods, Computer science, Task Scheduling, Algorithm, OpenFlow, High-Performance Computing, longest prefix match, Hardware and Architecture, Data compression, Electronic computers. Computer science, Computer Science, Physical Sciences, Reconfigurable Computing, Flow (mathematics), Mathematics, Dataflow Programming Languages

File Description: application/pdf

Access URL: https://doaj.org/article/fefc9292dfd14950940e34cc3f4215c6
https://hdl.handle.net/11250/3189338

Khronos: Fusing Memory Access for Improved Hardware RTL Simulation

Authors: Kexing Zhou, Yun Liang, Yibo Lin, Runsheng Wang, Ru Huang

Source: 56th Annual IEEE/ACM International Symposium on Microarchitecture. :180-193

Subject Terms: Parallel computing, Computer Networks and Communications, Flexibility (engineering), Graph, Theoretical computer science, Functional verification, Parallel Computing and Performance Optimization, FOS: Mathematics, Computer architecture, Embedded system, Design space exploration, Register-transfer level, Performance Optimization, Physics, Statistics, Logic gate, Optics, Simulation Platforms, Reconfigurable Computing Systems and Design Methods, Focus (optics), Computer science, Logic synthesis, Field-programmable gate array, Programming language, Algorithm, Formal verification, Networks on Chip in System-on-Chip Design, High-level synthesis, Hardware and Architecture, Computer Science, Physical Sciences, Debugging, Logic simulation, Mathematics

Segment-Aware Dynamic Partitioning PCM-DRAM: A Solution to IoT Devices Development Constraints

Authors: Qingyang Zhu, Liu Shu-yi, Zahid Akhtar, Kamran Siddique

Source: Journal of Computer Science. 19:1212-1221

Subject Terms: Computer Networks and Communications, Memristive Devices for Neuromorphic Computing, Internet of Things, Dynamic random-access memory, 7. Clean energy, Dram, Engineering, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, Electrical and Electronic Engineering, Phase change, Embedded system, Content-Centric Networking for Information Delivery, Phase-change memory, Computer network, Performance Optimization, Computer hardware, Engineering physics, Computer science, Distributed computing, Energy consumption, Semiconductor memory, Hardware and Architecture, Electrical engineering, Physical Sciences, Computer Science

Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation

Authors: Fernando Fernandes dos Santos, Luigi Carro, Paolo Rech

Contributors: Fernandes dos Santos, Fernando

Source: 2023 IEEE European Test Symposium (ETS). :1-10

Subject Terms: Parallel computing, [INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR], Artificial intelligence, General-purpose computing on graphics processing units, Convolutional neural network, Quantum mechanics, 7. Clean energy, Engineering, Computer engineering, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, GPU Computing, Electrical and Electronic Engineering, Performance Optimization, Physics, Reliability Evaluation, Simulation Platforms, Power (physics), Computer science, Profiling (computer programming), High-Performance Computing, Operating system, Fault Tolerance in Electronic Systems, Reliability (semiconductor), Hardware and Architecture, Physical Sciences, Computer Science, Graphics, Deep Learning in Computer Vision and Image Recognition, Computer Vision and Pattern Recognition

File Description: application/pdf

Access URL: https://hal.science/hal-04398063v1
https://doi.org/10.1109/itc51656.2023.00034
https://hal.science/hal-04398063v1/document

On vulnerabilities in EVT-based timing analysis: an experimental investigation on a multi-core architecture

Authors: Jamile Vasconcelos, George Lima, Marwan Wehaiba El Khazen, Adriana Gogonel, Liliana Cucu‐Grosjean

Contributors: Cucu-Grosjean, Liliana

Source: Design Automation for Embedded Systems. 28:1-21

Subject Terms: Parallel computing, Artificial intelligence, Probabilistic WCET (pWCET), Static timing analysis, Core (optical fiber), Extremes Value Theory (EVT), [INFO] Computer Science [cs], Multiprocessor Scheduling, Real-time computing, Visual arts, Multicore Architectures, Engineering, Inference, Architecture, Parallel Computing and Performance Optimization, FOS: Electrical engineering, electronic engineering, information engineering, FOS: Mathematics, GPU Computing, Electrical and Electronic Engineering, Embedded system, Probabilistic logic, Multi-core processor, Performance Optimization, Real-Time Scheduling in Embedded Systems, Extreme value theory, Statistics, Computer science, Measurement-Based Probabilistic Time Analysis (MBPTA), Real Time Systems (RTS), Algorithm, Fault Tolerance in Electronic Systems, Cache, Hardware and Architecture, Computer Science, Physical Sciences, Telecommunications, Worst Case Execution Time (WCET), Timing Analysis, FOS: Civil engineering, Art, Mathematics

File Description: application/pdf

Access URL: https://inria.hal.science/hal-04468516v1/document
https://doi.org/10.1007/s10617-023-09277-5
https://inria.hal.science/hal-04468516v1

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

Authors: Akhigbe-mudu Thursday Ehis

Source: Brazilian Journal of Science. 2:38-52

Subject Terms: Energy Efficiency, Memristive Devices for Neuromorphic Computing, Subthreshold conduction, 02 engineering and technology, 01 natural sciences, 7. Clean energy, Engineering, Power Management, 11. Sustainability, 0202 electrical engineering, electronic engineering, information engineering, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, 0101 mathematics, Electrical and Electronic Engineering, Embedded system, Electronic engineering, CMOS, Transistor, Voltage, Low-Power VLSI Circuit Design and Optimization, Computer science, Leakage Reduction, Programming language, Energy consumption, Low-Power, Hardware and Architecture, Electrical engineering, Physical Sciences, Computer Science, Software portability, Glitch

Vectorized and Parallel Computation of Large Smooth-Degree Isogenies using Precedence-Constrained Scheduling

Authors: Kittiphon Phalakarn, Vorapong Suppakitpaisarn, Francisco Rodríguez-Henríquez, M.A. Hasan

Source: Transactions on Cryptographic Hardware and Embedded Systems, Vol 2023, Iss 3 (2023)

Subject Terms: Parallel computing, Computer engineering. Computer hardware, Computer Networks and Communications, Distributed Constraint Optimization Problems and Algorithms, Information technology, 0102 computer and information sciences, 02 engineering and technology, Software optimization, 01 natural sciences, Mathematical analysis, 7. Clean energy, TK7885-7895, Multicore Architectures, Parallel Computing, Distributed Grid Computing Systems, Vectorization, Concurrency, Synchronization (alternating current), Elliptic curve, 0202 electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, FOS: Mathematics, GPU Computing, Precedence-constrained scheduling, Parallelism (grammar), Computer network, Multi-core processor, Performance Optimization, Mathematical optimization, Isogeny, T58.5-58.64, Heterogeneous Computing, Computer science, Distributed computing, Programming language, Algorithm, Isogeny-based cryptography, Isogeny computation, Hardware and Architecture, Channel (broadcasting), Implementation, Computer Science, Physical Sciences, Computation, Scheduling (production processes), Mathematics

Access URL: https://doaj.org/article/45f00fd79742494bb9182a839c972c7f

Energy efficient IPC based dual compression for endurance enhancement of NVRAM as main memory in embedded devices

Authors: Sakthivel Palanivelu, Saravana Kumar Radhakrishnan, C. Kumar, Sourav Barua, Hady H. Fayek

Source: IET Communications, Vol 17, Iss 11, Pp 1310-1320 (2023)

Subject Terms: Computer Networks and Communications, Memristive Devices for Neuromorphic Computing, TK5101-6720, Workload, 02 engineering and technology, Latency (audio), 7. Clean energy, Resistive Switching, Memory refresh, Engineering, Parallel Computing and Performance Optimization, FOS: Electrical engineering, electronic engineering, information engineering, 0202 electrical engineering, electronic engineering, information engineering, GPU Computing, Electrical and Electronic Engineering, Embedded system, energy conservation, Non-volatile random-access memory, Performance Optimization, Computer hardware, Computer science, Operating system, pattern matching, Non-volatile memory, Semiconductor memory, Hardware and Architecture, Distributed Storage Systems and Network Coding, Computer Science, Physical Sciences, Telecommunication, NAND Flash Memory, Telecommunications, Non-Volatile Memory, Computer memory

Access URL: https://doaj.org/article/3f36d81d0b93492db1e05fede3aa588c

Fast matrix multiplication via compiler‐only layered data reorganization and intrinsic lowering

Authors: Braedy Kuzma, Ivan Korostelev, João P. L. de Carvalho, José E. Moreira, Christopher Barton, Guido Araújo, José Nelson Amaral

Source: Software: Practice and Experience. 53:1793-1814

Subject Terms: FOS: Computer and information sciences, Parallel computing, Matrix multiplication, Composite material, Performance improvement, C.4, Computer Networks and Communications, Economics, Matrix (chemical analysis), Compiler, Set (abstract data type), Quantum mechanics, Quantum, Parallel Computing and Performance Optimization, FOS: Mathematics, GPU Computing, Key (lock), Code (set theory), Computer Science - Performance, Performance Optimization, Physics, Computational science, Heterogeneous Computing, Computer science, Materials science, Programming language, Performance (cs.PF), High-Performance Computing, Power Optimization, Operating system, Networks on Chip in System-on-Chip Design, Operations management, Computer Science - Distributed, Parallel, and Cluster Computing, Hardware and Architecture, Combinatorics, Distributed Storage Systems and Network Coding, Computer Science, Physical Sciences, Kernel (algebra), Supercomputer, Code generation, Distributed, Parallel, and Cluster Computing (cs.DC), Mathematics

Access URL: http://arxiv.org/abs/2305.18236

Response of HPC hardware to neutron radiation at the dawn of exascale

Authors: A. Bustos, C. Roy, R. H. Méndez, Sergio Rivera, Francisco Javier González, Xandra Campo, H. Asorey, Rafael Mayo-García

Source: Docu-menta. Repositorio Institucional del CIEMAT
Centro de Investigaciones Energéticas, Medioambientales y Tecnológicas (CIEMAT)

Subject Terms: Parallel computing, Computer Networks and Communications, induced failures, Computer science, 7. Clean energy, Radiation Effects, Exascale, Fault Tolerance in Electronic Systems, Engineering, Xeon Phi, silent errors, neutron radiation, Hardware and Architecture, HPC, Physical Sciences, Computer Science, 11. Sustainability, FOS: Electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, GPU Computing, Electrical and Electronic Engineering, atmospheric radiation, Distributed Fault Tolerance and Consistency in Systems

Access URL: http://documenta.ciemat.es/handle/123456789/2220

BaCO: A Fast and Portable Bayesian Compiler Optimization Framework

Authors: Erik Orm Hellsten, Artur Souza, Johannes Lenfers, Rubens Lacouture, Olivia Hsu, Adel Ejjeh, Fredrik Kjølstad, Michel Steuwer, Kunle Olukotun, Luigi Nardi

Source: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 4. :19-42

Subject Terms: FOS: Computer and information sciences, Parallel computing, Computer Science - Machine Learning, Artificial intelligence, Hyperparameter Optimization, Compiler, 02 engineering and technology, Bayesian probability, Learning with Noisy Labels in Machine Learning, Machine Learning (cs.LG), Artificial Intelligence, 0202 electrical engineering, electronic engineering, information engineering, Parallel Computing and Performance Optimization, GPU Computing, Computer architecture, Active Learning in Machine Learning Research, Bayesian optimization, Computer Science - Programming Languages, Computer Science - Performance, Performance Optimization, Computer science, Programming language, Performance (cs.PF), Hardware and Architecture, Optimizing compiler, Computer Science, Physical Sciences, Programming Languages (cs.PL)

Access URL: http://arxiv.org/abs/2212.11142

ParallelC-Assist: Productivity Accelerator Suite Based on Dynamic Instrumentation

Authors: Nachiketa Chatterjee, Srijoni Majumdar, Partha Pratim Das, Amlan Chakrabarti

Source: IEEE Access, Vol 11, Pp 73599-73612 (2023)

Subject Terms: Thread (computing), Computer Networks and Communications, Software quality, Software Diversity, Parallel Computing, Artificial Intelligence, Concurrency, Parallel Computing and Performance Optimization, Multi-threaded issues, Language-based Information Flow Security, Software engineering, Performance Optimization, Software development, Simulation Platforms, memory issues, dynamic instrumentation, Computer science, TK1-9971, Benchmarking, Operating system, Hardware and Architecture, 13. Climate action, Log Analysis and System Performance Diagnosis, Computer Science, Physical Sciences, Debugging, Electrical engineering. Electronics. Nuclear engineering, Software

Access URL: https://doaj.org/article/dde6018dfba14534b231f616312413bd

3D-DNaPE: Dynamic Neighbor-Aware Performance Enhancement for Thermally Constrained 3D Many-Core Systems

Authors: Mohammed S. Mohammed, Ahlam Al-Dhamari, Mosab Hamdan, Abdul-Malik H. Y. Saad, Antar Shaddad H. Abdul-Qawy, Muhammad Nadzir Marsono

Source: IEEE Access, Vol 11, Pp 131964-131978 (2023)

Subject Terms: Parallel computing, Performance improvement, Computer Networks and Communications, Memristive Devices for Neuromorphic Computing, Core (optical fiber), thermally constrained, Quantum mechanics, 7. Clean energy, Systems engineering, Multicore Architectures, Task (project management), Engineering, Computer engineering, 3D-stacked, Parallel Computing and Performance Optimization, FOS: Electrical engineering, electronic engineering, information engineering, GPU Computing, Electrical and Electronic Engineering, TK7885-7895 Computer engineer. Computer hardware, dark silicon, Multi-core processor, Performance Optimization, Physics, Power (physics), many-core system, performance enhancement, Computer science, Distributed computing, TK1-9971, Power Optimization, Networks on Chip in System-on-Chip Design, Cache, Operations management, Hardware and Architecture, Channel (broadcasting), Multi-core Processors, neighbor-aware, Computer Science, Physical Sciences, T58.6-58.62 Management information systems, Telecommunications, Electrical engineering. Electronics. Nuclear engineering

File Description: application/pdf

Access URL: https://doaj.org/article/31c186c35802474b8987c5c4114757fe

Quantization and Pipelined Hardware Implementation of Deep Neural Network Models

Authors: El Hadrami Cheikh Tourad, Mohsine Eleuldj

Source: Journal of Computer Science. 18:1021-1029

Subject Terms: Artificial neural network, Artificial intelligence, 02 engineering and technology, Latency (audio), 7. Clean energy, Deep Learning, Parallel Computing, Quantization (signal processing), Artificial Intelligence, Computer engineering, Design flow, Deep neural networks, Parallel Computing and Performance Optimization, 0202 electrical engineering, electronic engineering, information engineering, Neural Network Architectures, GPU Computing, Computer architecture, Embedded system, Performance Optimization, Computer hardware, Neural Network Fundamentals and Applications, Computer science, Field-programmable gate array, Algorithm, Hardware and Architecture, Computer Science, Physical Sciences, Telecommunications, Deep Learning in Computer Vision and Image Recognition, Computer Vision and Pattern Recognition

NextDenovo: an efficient error correction and accurate assembly tool for noisy long reads

Authors: Jiang Hu, Zhuo Wang, Zongyi Sun, Benxia Hu, Adeola Oluwakemi Ayoola, Fan Liang, Jingjing Li, José R. Sandoval, David N. Cooper, Kai Ye, Jue Ruan, Chuan-Le Xiao, Depeng Wang, Dong‐Dong Wu, Sheng Wang

Source: Genome Biol
Genome Biology, Vol 25, Iss 1, Pp 1-19 (2024)

Subject Terms: 0301 basic medicine, DNA Copy Number Variations, Regenerating Codes, QH301-705.5, Computer Networks and Communications, Segmental duplication, 0206 medical engineering, Evolutionary biology, 02 engineering and technology, Long reads, QH426-470, Error-correction, Gene, Computational biology, 03 medical and health sciences, Human genetics, Artificial Intelligence, Parallel Computing and Performance Optimization, Genetics, Humans, Biology (General), Genome Biology, Biology, Sequence assembly, Genome assembly, Genome, Genome, Human, Text Compression and Indexing Algorithms, Performance Optimization, 4. Education, Human genomes, High-Throughput Nucleotide Sequencing, Sequence Analysis, DNA, Genomics, Heterogeneous Computing, Nanopore Sequencing, High-Performance Computing, Hardware and Architecture, Distributed Storage Systems and Network Coding, FOS: Biological sciences, Computer Science, Physical Sciences, String Matching, Gene expression, Transcriptome, Software

Access URL: https://pubmed.ncbi.nlm.nih.gov/38671502
https://doaj.org/article/4730db7d79204aef83f6b00801455db6

Supporting single and multi-core resource access protocols on object-oriented RTOSes

Authors: Lucas Matheus dos Santos, Giovani Gracioli, Tomasz Kloda, Marco Caccamo

Contributors: Kloda, Tomasz, Federal University of Santa Caterina, Florianopolis, Brazil, Institut National des Sciences Appliquées (INSA), Équipe Verification de Systèmes Temporisés Critiques (LAAS-VERTICS), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Technische Universität Munchen - Technical University Munich - Université Technique de Munich (TUM)

Source: Design Automation for Embedded Systems. 27:31-50

Subject Terms: Economics, 0102 computer and information sciences, 02 engineering and technology, Multiprocessor Scheduling, 01 natural sciences, Priority ceiling protocol, Priority inheritance protocol, Resource Allocation, Multicore Architectures, Parallel Computing and Performance Optimization, RTOS, 0202 electrical engineering, electronic engineering, information engineering, Real-time operating systems, Embedded system, Real-time systems, Real-time operating system, Performance Optimization, Real-Time Scheduling in Embedded Systems, Reconfigurable Computing Systems and Design Methods, Computer science, Distributed computing, [INFO.INFO-ES] Computer Science [cs]/Embedded Systems, Resource access protocols, Overhead (engineering), Operating system, Operations management, Hardware and Architecture, Computer Science, Physical Sciences, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, MrsP, Scheduling (production processes), Stack resource policy

File Description: application/pdf