Performance comparison of 16-bit and 32-bit RISC (reduced instruction set computer) pipelined processors - A Verilog-based design and analysis.

Authors: Tejaswini, Dasari¹ (AUTHOR) tejaswini.lvs22@bmsce.ac.in, Shrisha, M. R.¹ (AUTHOR) shrishamr.ece@bmsce.ac.in

Source: AIP Conference Proceedings. 2026, Vol. 3359 Issue 1, p1-10. 10p.

Subject Terms: *Reduced instruction set computers, *Microprocessor design & construction, *Verilog (Computer hardware description language), *Computer architecture, *Computer performance, *Floating-point arithmetic

一种面向嵌入式场景的五级流水线 RISC-V 处理器设计.

Alternate Title: Design of five-stage pipelined RISC-V processor for embedded scenarios.

Authors: 于安宁^1,2, 黄 晗^1,2, 利 节^1,2, 曾孝平³

Source: Application Research of Computers / Jisuanji Yingyong Yanjiu. Sep2026, Vol. 43 Issue 9, p2767-2772. 6p.

Subject Terms: *Microprocessor design & construction, *Embedded computer systems, *Internet of things, *Verilog (Computer hardware description language)

A comprehensive review on implementation analysis of 5-Stage pipelined RISC-V processor.

Authors: Vaishnavi, C. M.¹ (AUTHOR) vaishnavicm03@gmail.com, Trupti, R.¹ (AUTHOR) trupti11ravi04@gmail.com, Asuti, Manjunath G.¹ (AUTHOR) manjunathasuti@bnmit.in, Munavalli, Jyoti R.¹ (AUTHOR) jyotirmunavalli@bnmit.in

Source: AIP Conference Proceedings. 2026, Vol. 3426 Issue 1, p1-6. 6p.

Subject Terms: *Microprocessor design & construction, *Reduced instruction set computers

Design and Optimization of a Low-Power RISC-V Processor for NDIR Measurement of CO2 Levels

Authors: Núñez Prieto, Ricardo

Thesis Advisors: Avellana Tarrats, Narcis, Castells Rufas, David, Teres Teres, Lluis Antoni

Source: TDX (Tesis Doctorals en Xarxa)

Subject Terms: Disseny de microprocessadors, Microprocessor design, Diseño de microprocesadores, Risc-V, Baix consum, Low-power, Bajo consumo, Tecnologies

Time: 621.3

File Description: application/pdf

Access URL: http://hdl.handle.net/10803/691324

Standard cell library based processor design using MGDI technique.

Authors: S, Shankar¹ (AUTHOR), S, Balamurali² (AUTHOR), P, Sasipriya³ (AUTHOR), Angeline A, Anita³ (AUTHOR) anitaangeline.a@vit.ac.in

Source: International Journal of Electronics. Mar2026, Vol. 113 Issue 3, p465-478. 14p.

Subject Terms: Microprocessor design & construction, Reduced instruction set computers, Power measurement (Electricity), Multidisciplinary design optimization, Computer performance

Design and HDL Implementation of a Pipelined 8-bit Microprocessor

Authors: Pyasi, Chetan, Singh, H. Manas

Source: 2025 IEEE Silchar Subsection Conference (SILCON) Silchar Subsection Conference (SILCON), 2025 IEEE. :1-6 Nov, 2025

Relation: 2025 IEEE Silchar Subsection Conference (SILCON)

Post-Silicon Debugging via Hierarchical Signal Reporting

Authors: Suryawan, Fajar

Source: 2025 IEEE International Conference on Signals and Systems (ICSigSys) Signals and Systems (ICSigSys), 2025 IEEE International Conference on. :90-94 Nov, 2025

Relation: 2025 IEEE International Conference on Signals and Systems (ICSigSys)

Analysis of coprocessor-based acceleration for hardware-based semaphore concurrency control.

Authors: Walichiewicz, Michal¹ michal.walichiewicz@protonmail.com, Milik, Adam¹ adam.milik@polsl.pl

Source: International Journal of Electronics & Telecommunications. 2026, Vol. 72 Issue 3, p1-9. 9p.

Subject Terms: *Synchronization, *Microprocessor design & construction, *Parallel programming

深度学习处理器: 人工智能芯片 基础研究之路.

Alternate Title: Deep learning processor: Road to fundamental research on AI chip.

Authors: 陈云霁¹ cyj@ict.ac.cn

Source: Bulletin of the Chinese Academy of Sciences / Chung-kuo ko Hsueh Yuan Yuan Kan. Jun2026, Vol. 41 Issue 6, p1276-1288. 13p.

Subject Terms: *Microprocessors, *Microprocessor design & construction, *Artificial intelligence, *Scientific method, *Computer engineering

Company/Entity: Chinese Academy of Sciences (Beijing, China)

深度驱动图划分的关键路径延时优化研究.

Alternate Title: Depth-driven graph partitioning for critical path delay optimization.

Authors: 余学雯^1,2 xwyu18@163.com, 陈海燕^1,2 hychen608@163.com, 黄鹏程^1,2 huang.pc20@nudt.edu.cn

Source: Computer Engineering & Science / Jisuanji Gongcheng yu Kexue. Apr2026, Vol. 48 Issue 4, p590-598. 9p.

Subject Terms: *Microprocessor design & construction, *Directed acyclic graphs, *Electronic design automation, *Logic circuits, *Mathematical optimization

A Tiny Processor with Rapid Interrupt Response for AI Accelerator Control

Authors: Cui, Yang, Xiong, Jie, Yang, Zhuo, Zhang, Li

Source: 2024 4th International Conference on Electronic Information Engineering and Computer Communication (EIECC) Electronic Information Engineering and Computer Communication (EIECC), 2024 4th International Conference on. :1281-1284 Dec, 2024

Relation: 2024 4th International Conference on Electronic Information Engineering and Computer Communication (EIECC)

A Novel ALU Architecture Implementation using a Sub-Threshold Adiabatic Logic Design for Low-Power Processors.

Authors: Anitha, A.^1,2 (AUTHOR) aniravi08@gmail.com, Rooban, S.³ (AUTHOR) yes.rooban@gmail.com

Source: IETE Journal of Research. Dec2025, Vol. 71 Issue 12, p4136-4152. 17p.

Subject Terms: *Microprocessor design & construction, *Logic design, *Semiconductor technology, *Complementary metal oxide semiconductors, *Very large scale circuit integration, *Microprocessors, *Energy consumption

Vektör hızlandırıcılı işlemci tasarımı.

Alternate Title: Processor design with vector accelerator.

Authors: Çakır, Abdülkadir¹, Çakacı, Necati² necaticakaci@outlook.com

Source: International Journal of Technological Sciences / Uluslararasi Teknolojik Bilimler Dergisi. Dec2025, Vol. 17 Issue 2, p20-27. 8p.

Subject Terms: *Field programmable gate arrays, *Microprocessor design & construction, *Reduced instruction set computers, *Array processors, *Embedded computer systems, *Scalability, *Logic design, *Computer performance

P‐.9.13: A GD32 MCU‐Integrated LCD Module with Abnormality Detection Capability.

Authors: Ren, Kairui, Liu, Yujie, Sun, Yaxin, Chen, Xiuyun, Wang, Guangquan

Source: SID Symposium Digest of Technical Papers; Aug2026 Supplement 1, Vol. 57, p1644-1647, 4p

Subject Terms: Microcontrollers, Liquid crystal displays, Flat panel displays, Microprocessor design & construction, Outlier detection, System integration

TALOS: An Ultra-Efficient Area-Space 6G CryptoProcessor Leveraging Reusable Hardware Security Modules.

Authors: Bikos, Anastasios N.

Source: Journal of Cybersecurity & Privacy; Aug2026, Vol. 6 Issue 4, p122, 62p

Subject Terms: Cryptography, Hardware design & construction, Stream ciphers, Microprocessor design & construction, Advanced Encryption Standard

Research on low-power microprocessor design and optimization technology

Authors: Zhang, Yiqun, Zhang, Shuai, Feng, Luyao

Source: 2024 International Conference on Power, Electrical Engineering, Electronics and Control (PEEEC) PEEEC Power, Electrical Engineering, Electronics and Control (PEEEC), 2024 International Conference on. :362-366 Aug, 2024

Relation: 2024 International Conference on Power, Electrical Engineering, Electronics and Control (PEEEC)

[formula omitted]RVFormal: Formal verification of RISC-V processor Chisel designs.

Authors: Shen, Shidong^1,2 (AUTHOR) shensd@ios.ac.cn, Chen, Shijie^1,2 (AUTHOR) chensj@ios.ac.cn, Liu, Yicheng^1,2 (AUTHOR) liuyc@ios.ac.cn, Zhang, Lijun^1,2 (AUTHOR) zhanglj@ios.ac.cn, Song, Fu^1,2,3 (AUTHOR) songfu@ios.ac.cn, Wu, Zhilin^1,2 (AUTHOR) wuzl@ios.ac.cn

Source: Journal of Systems Architecture. Jun2026, Vol. 175, pN.PAG-N.PAG. 1p.

Subject Terms: *Parallel processing, Microprocessor design & construction, Formal methods (Computer science), Computer hardware description languages, Reduced instruction set computers

Applications of STM32 and ESP32 in Modern Embedded Systems.

Authors: Biradar, A. M., Dandare, Renuka Uday

Source: International Scientific Journal of Engineering & Management; Jul2026, Vol. 5 Issue 7, p1-4, 4p

Subject Terms: Microcontrollers, Internet of things, Automation, Microprocessor design & construction, Embedded computer systems, Wireless Internet

Design and Optimization of a RISC-V Processor for Modern Applications.

Authors: Dey, Annesha, Sarma, Manprita, Rajput, Rohit, Bhowmick, Brinda

Source: Grenze International Journal of Engineering & Technology (GIJET); Jun2026, Vol. 12 Issue 2, p3958-3964, 7p

Subject Terms: Microprocessor design & construction, Instruction set architecture, Data pipelining, Edge computing, Benchmark problems (Computer science), Mathematical optimization

Design and Physical Implementation of Custom RISCV Processor from RTL to GDSII.

Authors: N., Prajwal, K., Nakul Shetty

Source: Grenze International Journal of Engineering & Technology (GIJET); Jun2026, Vol. 12 Issue 2, p3702-3708, 7p

Subject Terms: Microprocessor design & construction, Integrated circuit design, Reduced instruction set computers, Floating-point arithmetic, Electronic design automation, Computer arithmetic, Scientific computing