Effect of Transient Failures on FPGA-based Heterogeneous Multicore System Scheduling

Authors: Alansary, Kareem, Amer, Hassanein, Salama, Cherif

Source: 2022 4th Novel Intelligent and Leading Emerging Sciences Conference (NILES) Novel Intelligent and Leading Emerging Sciences Conference (NILES), 2022 4th. :256-259 Oct, 2022

Relation: 2022 4th Novel Intelligent and Leading Emerging Sciences Conference (NILES)

Federated Scheduling Optimization Scheme for Typed Tasks With Power Constraints in Heterogeneous Multicore Processor Architectures

Authors: Wen, X., Liu, G., Li, D., Yu, Y., Zhao, H., Huang, T.

Source: IEEE Access Access, IEEE. 11:85728-85746 2023

Resource-Aware Partitioned Scheduling for Heterogeneous Multicore Real-Time Systems

Authors: Han, Jian-Jun, Cai, Wen, Zhu, Dakai

Source: 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC) Design Automation Conference (DAC), 2018 55th ACM/ESDA/IEEE. :1-6 Jun, 2018

Relation: 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

Reliability-Aware Scheduling on Heterogeneous Multicore Processors

Authors: Naithani, Ajeya, Eyerman, Stijn, Eeckhout, Lieven

Source: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) HPCA High Performance Computer Architecture (HPCA), 2017 IEEE International Symposium on. :397-408 Feb, 2017

Relation: 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA)

Cross-Layer Exploration of Heterogeneous Multicore Processor Configurations

Authors: Sarma, Santanu, Dutt, Nikil

Source: 2015 28th International Conference on VLSI Design VLSI Design (VLSID), 2015 28th International Conference on. :147-152 Jan, 2015

Relation: 2015 28th International Conference on VLSI Design (VLSID)

Energy efficient scheduling with probability and task migration considerations for soft real-time systems

Authors: Ying Li, Jianwei Niu, Xiang Long, Meikang Qiu

Source: 2014 IEEE Computers, Communications and IT Applications Conference Computing, Communications and IT Applications Conference (ComComAp), 2014 IEEE. :287-293 Oct, 2014

Relation: 2014 IEEE Computing, Communications and IT Applications Conference (ComComAp)

Core Performance Based Packet Priority Router for NoC-Based Heterogeneous Multicore Processor

Authors: Indragandhi, K.^Aff18, Jawahar, P. K.^Aff18

Contributors: Kacprzyk, Janusz, Series Editor^Aff1, Pal, Nikhil R., Advisory Editor^Aff2, Bello Perez, Rafael, Advisory Editor^Aff3, Corchado, Emilio S., Advisory Editor^Aff4, Hagras, Hani, Advisory Editor^Aff5, Kóczy, László T., Advisory Editor^Aff6, Kreinovich, Vladik, Advisory Editor^Aff7, Lin, Chin-Teng, Advisory Editor^Aff8, Lu, Jie, Advisory Editor^Aff9, Melin, Patricia, Advisory Editor^Aff10, Nedjah, Nadia, Advisory Editor^Aff11, Nguyen, Ngoc Thanh, Advisory Editor^Aff12, Wang, Jun, Advisory Editor^Aff13, Satapathy, Suresh Chandra, editor^Aff14, Bhateja, Vikrant, editor^Aff15, Janakiramaiah, B., editor^Aff16, Chen, Yen-Wei, editor^Aff17

Source: Intelligent System Design : Proceedings of Intelligent System Design: INDIA 2019. 1171:389-397

Hybrid fuzzy-based Deep Remora Reinforcement Learning Based Task Scheduling in Heterogeneous Multicore-processor

Authors: Gupta, Sachi ^{a, ⁎}, Agarwal, Gaurav ^b

Source: In Microprocessors and Microsystems July 2022 92

Predictive Heterogeneity-Aware Application Scheduling for Chip Multiprocessors

Authors: Chen, Jian, Nair, Arun Arvind, John, Lizy K.

Source: IEEE Transactions on Computers IEEE Trans. Comput. Computers, IEEE Transactions on. 63(2):435-447 Feb, 2014

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

Authors: Kondo, H., Nakajima, M., Masui, N., Otani, S., Okumura, N., Takata, Y., Nasu, T., Takata, H., Higuchi, T., Sakugawa, M., Fujiwara, H., Ishida, K., Ishimi, K., Kaneko, S., Itoh, T., Sato, M., Yamamoto, O., Arimoto, K.

Source: IEEE Journal of Solid-State Circuits IEEE J. Solid-State Circuits Solid-State Circuits, IEEE Journal of. 43(4):892-901 Apr, 2008

Using DVFS and task scheduling algorithms for a hard real-time heterogeneous multicore processor environment

Authors: Kim, Sung Il, Kim, Hwan Tae, Kang, Gyu Seong, Kim, Jong-Kook

Source: Proceedings of the 2013 workshop on Energy efficient high performance parallel and distributed computing. :23-30

Availability: http://dl.acm.org/doi/10.1145/2480347.2480350

Power Efficiency Evaluation of Block Ciphers on GPU-Integrated Multicore Processor

Authors: Nishikawa, Naoki^Aff22, Iwai, Keisuke^Aff22, Kurokawa, Takakazu^Aff22

Contributors: Hutchison, David, editor^Aff1, Kanade, Takeo, editor^Aff2, Kittler, Josef, editor^Aff3, Kleinberg, Jon M., editor^Aff4, Mattern, Friedemann, editor^Aff5, Mitchell, John C., editor^Aff6, Naor, Moni, editor^Aff7, Nierstrasz, Oscar, editor^Aff8, Pandu Rangan, C., editor^Aff9, Steffen, Bernhard, editor^Aff10, Sudan, Madhu, editor^Aff11, Terzopoulos, Demetri, editor^Aff12, Tygar, Doug, editor^Aff13, Vardi, Moshe Y., editor^Aff14, Weikum, Gerhard, editor^Aff15, Xiang, Yang, editor^Aff16, Stojmenovic, Ivan, editor^Aff17, Apduhan, Bernady O., editor^Aff18, Wang, Guojun, editor^Aff19, Nakano, Koji, editor^Aff20, Zomaya, Albert, editor^Aff21

Source: Algorithms and Architectures for Parallel Processing : 12th International Conference, ICA3PP 2012, Fukuoka, Japan, September 4-7, 2012, Proceedings, Part I. 7439:347-361

Programming the Cell Processor

Authors: Kessler, Christoph, 1966

Source: Fundamentals of Multicore Software Development Chapman & Hall/CRC computational science series. :155-198

Subject Terms: parallel programming, Cell Broadband Engine, heterogeneous multicore processor

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91497

Optimization of Collective Communication in Intra-cell MPI

Authors: Velamati, M. K.^Aff1, Kumar, A.^Aff1, Jayam, N.^Aff1, Senthilkumar, G.^Aff1, Baruah, P. K.^Aff1, Sharma, R.^Aff1, Kapoor, S.^Aff2, Srinivasan, A.^Aff3

Contributors: Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Aluru, Srinivas, editor, Parashar, Manish, editor, Badrinath, Ramamurthy, editor, Prasanna, Viktor K., editor

Source: High Performance Computing – HiPC 2007 : 14th International Conference, Goa, India, December 18-21, 2007. Proceedings. 4873:488-499

Partition Scheduling on Heterogeneous Multicore Processors for Multi-dimensional Loops Applications

Authors: Wang, Yan, Li, Kenli, Li, Keqin

Source: International Journal of Parallel Programming. August 2017 45(4):827-852

Programming Techniques for the Cell Processor

Authors: Kessler, Christoph, 1966

Source: it - Information Technology. 53(2):66-74

Subject Terms: parallel programming, Cell Broadband Engine, heterogeneous multicore processor

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-91493

Optimized On-Chip Pipelining of Memory-Intensive Computations on the Cell BE

Authors: Kessler, Christoph, 1966, Keller, Jörg

Source: VR Integrated Software Pipelining SSF DSP Platform for Emerging Applications in Telecommunication and Multimedia ACM SIGARCH Computer Architecture News. 36(5):36-45

Subject Terms: Heterogeneous multicore processor, Cell Broadband Engine, Pipelining, Parallel computing, Stream computing, Mapping, Integer Linear Programming, Program optimization, TECHNOLOGY, Information technology, Computer science, TEKNIKVETENSKAP, Informationsteknik, Datavetenskap

File Description: print

Access URL: https://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-52029

Periodic activity migration for fast sequential execution in future heterogeneous multicore processors

Authors: Michaud, Pierre

Contributors: Compilation, parallel architectures and system (CAPS), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)

Source: https://inria.hal.science/inria-00340566 ; [Research Report] PI 1909, 2008, pp.20.

Subject Terms: Heterogeneous multicore processor, power consumption, heat flux, periodic activity migration, ACM: C.: Computer Systems Organization/C.1: PROCESSOR ARCHITECTURES, [INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR]

Relation: Report N°: PI 1909

Availability: https://inria.hal.science/inria-00340566
https://inria.hal.science/inria-00340566/document
https://inria.hal.science/inria-00340566/file/PI-1909.pdf

Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators

Authors: Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA, Yasuhiro TAKEI

Source: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2013, E96.A(12):2576

Resource management for efficient single-ISA heterogeneous computing

Authors: Chen, Jian, doctor of electrical and computer engineering

Subject Terms: Performance modeling, Heterogeneous multicore processor, Hardware resource demand, Application scheduling, Resource management

File Description: application/pdf

Availability: http://hdl.handle.net/2152/ETD-UT-2011-05-3160