Model-Based Proactive Read-Validation in Transaction Processing Systems

Authors: Economo, Simone, Silvestri, Emiliano, Di Sanzo, Pierangelo, Pellegrin, Alessandro, Quaglia, Francesco

Source: 2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS) Parallel and Distributed Systems (ICPADS), 2018 IEEE 24th International Conference on. :481-488 Dec, 2018

Relation: 2018 IEEE 24th International Conference on Parallel and Distributed Systems (ICPADS)

Prompt application-transparent transaction revalidation in software transactional memory

Authors: Economo, Simone, Silvestri, Emiliano, Di Sanzo, Pierangelo, Pellegrini, Alessandro, Quaglia, Francesco

Source: 2017 IEEE 16th International Symposium on Network Computing and Applications (NCA) Network Computing and Applications (NCA), 2017 IEEE 16th International Symposium on. :1-6 Oct, 2017

Relation: 2017 IEEE 16th International Symposium on Network Computing and Applications (NCA)

Preemptive Software Transactional Memory

Authors: Silvestri, Emiliano, Economo, Simone, Di Sanzo, Pierangelo, Pellegrini, Alessandro, Quaglia, Francesco

Source: Proceedings of the 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing. :294-303

Availability: http://dl.acm.org/doi/10.1109/CCGRID.2017.98

Configurable and Efficient Memory Access Tracing via Selective Expression-Based x86 Binary Instrumentation

Authors: Economo, Simone, Cingolani, Davide, Pellegrini, Alessandro, Quaglia, Francesco

Source: 2016 IEEE 24th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS) Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS), 2016 IEEE 24th International Symposium on. :261-270 Sep, 2016

Relation: 2016 IEEE 24th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS)

A Toolchain to Verify the Parallelization of OmpSs-2 Applications

Authors: Economo, Simone^{Aff10, Aff11}, Royuela, Sara^Aff10, Ayguadé, Eduard^Aff10, Beltran, Vicenç^Aff10

Contributors: Goos, Gerhard, Founding Editor^Aff1, Hartmanis, Juris, Founding Editor^Aff2, Bertino, Elisa, Editorial Board Member^Aff3, Gao, Wen, Editorial Board Member^Aff4, Steffen, Bernhard, Editorial Board Member^Aff5, Woeginger, Gerhard, Editorial Board Member^Aff6, Yung, Moti, Editorial Board Member^Aff7, Malawski, Maciej, editor^Aff8, Rzadca, Krzysztof, editor^Aff9

Source: Euro-Par 2020: Parallel Processing : 26th International Conference on Parallel and Distributed Computing, Warsaw, Poland, August 24–28, 2020, Proceedings. 12247:18-33

A toolchain to verify the parallelization of OmpSs-2 applications

Authors: Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors, Barcelona Supercomputing Center, Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions, Economo, Simone, Royuela Alcázar, Sara, Ayguadé Parra, Eduard, Beltran Querol, Vicenç

Index Terms: Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors, Parallel programming (Computer science), Compilers (Computer programs), Computer programs -- Testing, Synchronization, Software testing and debugging, Programació en paral·lel (Informàtica), Compiladors (Programes d'ordinador), Programes d'ordinador -- Control de qualitat, Conference report

URL: https://hdl.handle.net/2117/330464
https://link.springer.com/chapter/10.1007/978-3-030-57675-2_2
https://link.springer.com/chapter/10.1007/978-3-030-57675-2_2
info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII
info:eu-repo/grantAgreement/EC/H2020/871669/EU/A Model-driven development framework for highly Parallel and EneRgy-Efficient computation supporting multi-criteria optimisation/AMPERE
info:eu-repo/grantAgreement/EC/H2020/730897/EU/Transnational Access Programme for a Pan-European Network of HPC Research Infrastructures and Laboratories for scientific computing/HPC-EUROPA3
info:eu-repo/grantAgreement/MINECO//SEV-2015-0493/ES/BARCELONA SUPERCOMPUTING CENTER - CENTRO. NACIONAL DE SUPERCOMPUTACION