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    Academic Journal

    Source: The Herald of the Siberian State University of Telecommunications and Information Science; Том 17, № 2 (2023); 69-83 ; Вестник СибГУТИ; Том 17, № 2 (2023); 69-83 ; 1998-6920

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    Relation: https://vestnik.sibsutis.ru/jour/article/view/759/722; DiStefano T. H., Shatzkes M. Impact ionization model for dielectric instability and breakdown // Appl. Phys. Lett. 1974. V. 25. P. 685–687.; Solomon P. Breakdown in silicon oxide – a review // J. Vac. Sci. Technol. 1977. V. 14. P. 1122–1130.; Klein N. Electrical breakdown mechanisms in thin insulators // Thin Solid Films. 1978. V. 50. P. 223–232.; Yeo Y. C., King T. J., Hu C. MOSFET Gate Leakage Modeling and Selection Guide for Alternative Gate Dielectrics Based on Leakage Considerations // IEEE Transactions on Electron Devices. 2003. V. 50, № 4. P. 1027–1035.; Hastings A. The Art of Analog Layout. New Jersey: Pearson Prentice Hall, 2006. 648 p. 6. Fowler R. H., Nordheim L. Electron emission in intense electric fields // Proc. R. Soc. London, Ser. A. 1928. V. 119. P. 173–181.; Larcher L., Passagnella A., Ghidman G. A Model of the Stress Induced Leakage Current in Gate Oxides // IEEE Trans. Electron Devices. 2001. V. 48, № 2. P. 285–288.; Lenahan P. M., Mele J. J., Campbell J. P., Kang A. Y., Lowry R. K., Woodbury D., et al. Direct Experimental Evidence Linking Silicon Dangling Bond Defects to oxide Leakage Currents // Proc. International Reliability Physics Symp. 2001. P. 150–155.; Яворский Б. М., Детлаф А. А., Лебедев А. К. Справочник по физике для инженеров и студентов вузов / изд. 8-е, перераб. и испр. М.: Оникс; Мир и Образование, 2006. 1056 с.; Ker Ming-Dou, Yuan-Wen Hsiao. CDM ESD Protection in CMOS Integrated Circuits // Proc. The Argentine School of Micro-Nanoelectronics, Technology and Applications, 2008. P. 61–65.; Henry L., Barth J., Hyatt H., at al. Charged device model metrology: limitations and problems // Microelectron. Reliab. Jun. 2002. V. 42, № 6. P. 919–927.; Dabral S., Maloney T. J. Basic ESD and I/O Design. Toronto: John Wiley & Sons Inc. 1998. V. XIII. 328 p.; Chen J. Z., Amerasekera A., Duvvury Ch. Design Methodology for Optimizing Gate Driven ESD Protection Circuits in Submicron CMOS Processes // Proc. EOS/ESD Symp., 1997. P. 1–10.; Richier C., Salome P., Mabboux G., at al. Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 m CMOS process // Proc. EOS/ESD Symp., Sep. 2000. P. 251–259.; Clein D. CMOS IC LAYOUT. Concepts, methodologies and tools. Boston: Newnes. 2000. № XV. 261 p.; Razavi B. Design of Analog CMOS Integrated Circuits. McGraw-Hill Education. NY, 2017. 782 p.; https://vestnik.sibsutis.ru/jour/article/view/759

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    Academic Journal

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    Relation: Немченко Ю. С. Прогнозирование возможности проведения в НИПКИ "Молния" испытания объектов военной техники на электромагнитную совместимость по стандартам НАТО / Ю. С. Немченко // Вісник Нац. техн. ун-ту "ХПІ" : зб. наук. пр. Сер. : Техніка та електрофізика високих напруг = Bulletin of National Technical University "KhPI" : coll. works. Ser. : Technique and Electrophysics of High Voltage. – Харків : НТУ "ХПІ", 2017. – № 15 (1237). – С. 84-91.; http://repository.kpi.kharkov.ua/handle/KhPI-Press/29116

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